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PLL-free clock generator, fully on-chip

I'm looking for:

A VCO chip where all the VCO components are on-chip, in other words I feed it some control voltage and it produces an output frequency. I don't want any external components like R/L/Cs or crystals that might have harmonics of the output frequency on them.

Broadband: something like 0-1000MHz, where '0' and '1000' are fairly flexible. But not a range like 215-270MHz. A stepped range would be OK if there were enough steps. I don't mind (in fact it'd be quite useful) if the output was a divided form of the internal clock.

Don't care if it's linear or not, as long as it's stable enough that I can draw a V/f graph.

The ability to keep the oscillator running but switch off the output pin.

No PLL.

It doesn't /have/ to be a VCO - if there's some other way to generate a frequency on-chip that doesn't use a PLL that would be fine (ring oscillators?).

Preferably plastic package.

It's only for experimental purposes so cost, board space etc isn't too much of an issue.

Don't care about supply voltage or logic levels

I'm quite happy to use some chip that uses an onboard oscillator for other things internally, as long as I can turn on and off the clock on an output pin.

This sounds like a nuts request, but I have a genuine reason for wanting this :)

Something like the DS1085 looks perfect, except its top-end frequency is much lower than I'd like. Any other suggestions?

Thanks Theo

Reply to
Theo Markettos
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OK.

I think you're out of luck then... Analog Devices has some 1GHz DDSes that would get you, say, 0-400MHz and you could multiply or mix the output to get a broader range, and the spurious-free dynamic range (SFDR) isn't as good as more conventional PLL-based generators (although this might not be a problem for you).

For experimental purposes could you just pick up a cheap wideband function generator on eBay? :-)

Reply to
Joel Koltner

Well, 1GHz isn't exactly a hard requirement but 'more than 133MHz' is. It'll just set the upper limit on the measurements I make. 400MHz would be OK.

Thanks for the ref to Analog's DDSes (I didn't know Direct Digital Synthesis - another handy Google word :). But they seem to have PLLs in them, unless I'm missing something?

Needs to be a chip, preferably in a plastic package, I'm afraid :)

My current idea is a series of ring oscillators in an FPGA. Jittery like anything but I don't care about medium/long term drift. It's 'just' a case of bending the tools to synthesise them. And I haven't a clue what sort of frequency I might get...

Theo

Reply to
Theo Markettos
[...]

I am not very familiar with FPGA and what resources they offer. If they feature OC drivers where the input can be routed to a pin and where there preferably is just one ("unbuffered") inverter stage involved instead of the usual three:

Set up a ring oscillator, route an OC output to each tap. Control the OC inputs from PWMs that are nicely RC filtered. The PWM then controls the frequency. Rather crude though, kind of a broomstick solution. If the Rs and Cs bother you maybe use 0201 sizes ;-)

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Regards, Joerg

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Reply to
Joerg

Hmm... that's an interesting idea. I might think about that, thanks. Or if there's any other ways to do analogue control voltages to the FPGA (like mess with the power rails).

Theo

Reply to
Theo Markettos

Sure, if there is nothing else important on that FPGA that could get messed up and it's not one of those newfangled FPGA with umpteen supplies that must be babied. You can change the frequency of a ring oscillator widely via VCC scooting. Take a look at prop delay versus VCC at the end of page 4:

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Regards, Joerg

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Joerg

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