Antti Lukats: all my past live projects to be published...

type,

few

netlist

VHDL.

code

I think you have missed the point. I make absolutely no mention of EDK IP.

First with respect to the PCI logicore, which if purchased from Xilinx is provided with an EDF netlist, and a VHDL netlist (or as some would say "structural VHDL") that instantiates this core netlist, the IO pins, and a user configurable module. To use this entire package, without editing any of the IP core from the vendor, which is delivered as both VHDL and a netlist, one must do as I described. This still requires some editing of the contraints that are provided by the vendor, but only for location in the hierarchy.

Secondly, DDR SDRAM was cited as an example because separating out the tristate buffer from the DDR register is counter to the architecture of the FPGA. The IO cell in virtex2 contatains a tristate buffer and a DDR register, each of which only exist in this type of cell. Breaking off the tristate buffer from the DDR register does not provide for any sort of meaningful improvement in the hierarchy. Rather, it confuses the issue. Arguments for breaking the hierarchy at this point that have been presented in this newsgroup are: using chipscope at the top level of a hierarchy; or the creation of a vendor agnostic design. Given that the signal between the DDR register and the OBUF, or the IBUF and the other DDR register are not observable, as the wires simply do not exist in the architecture, obviates the first argument. The fact that the DDR register and the IO buffer are both vendor specific, and vendor unique, obviates the second argument.

As the FPGAs get more encompassing IO structures, as with V4, it makes more and more sense to bind the IO structures which will include shift register, differential pins, etc, into the cores themselves. One is kidding himself if he believes he can do a high performance and cost effective design without expressly instantiating specific architectural elements. The IO structures are no exception.

This is not to say what Xilinx did with the EDK and separating out tristates did not make sense. It did, when specific IO pin types and IO structures did not need to be called out from the underlying core. For example, many people new to FPGAs and the coreconnect bus architecture have started by using the GPIO module to interface to their own IP inside the chip. This is a good example of where one may want to use the same IP for on chip or off chip interconnect, and as such, not binding the IO pins to the core results in one rather than two cores being created.

Regards, Erik.