Hi, there:
My ASIC library doesn't allow 1) input pins of any cells left unconnected,
2) multiple input pins of same cell connected to same signal net.
Though 2nd appear quite abscure, since these multiple input pins waste too many vdd/gnd cells.
My library has special tie-high/low cells to cater these circumstances, but what are the constants in Design Compiler that I can set in order to comply with these two rules?
Thanks