I2C Slave

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I am searching a synthesizable I2C Slave model in VHDL.
Does somebody know where I can find it?


Regards, Matija

Re: I2C Slave
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Did you check opencores.org?  That is always a good place to start.
They have a lot of IO peripherals available.  


Rick "rickman" Collins

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Re: I2C Slave
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Be careful, though, Matija, the I2C slave core in OpenCores has significant
errors.  I used it and had to debug it to the point that I totally
synchronized it, with the exception of the microprocessor interface of
course, in order for it to work properly.  Unfortunately I cannot send you
this design, because all of my work belongs to my client company, as they
paid for my efforts.  The OpenCores designs apparently are someone's pet
academic projects that aren't really being used in the real world.  They
come close but no enchilada.

I don't know if you are using Xilinx, but they have a I2C core that I would
investigate if I were doing it over again.

Good luck.

Simon Ramirez, Consultant
Oviedo, FL  USA
Synchronous Design , Inc.
Xilinx XPERTS Partner

Re: I2C Slave

Simon , can You send me your e-mail adress?I try to reply  You direct but
that don't work


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Re: I2C Slave

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I looked around for the same but written in Verilog.  Never found one
(I looked at the opencores master model but I don't trust it), so I
ended up writing one.

Part of the complication is what kind of slave you're trying to
implement.  For example, imagine you'd like to simply implement an I2C
slave RAM.  That differs from, say, implementing a clone of the
Philips PCF8574 8-bit I/O expander.

My design required that an external master read and write a handful of
registers in my FPGA.  It's one of those deals where you have to write
the address of the first register (an eight-bit number, for a total of
256 possible register), then you can essentially burst read or write
from there.

Basically, the I2C Slave Module itself has an eight-bit address
register output, an eight-bit output port (where data written by the
master appears), an eight-bit data input port (where data to be read
by the master must be driven) and a single bit "WriteDataValid"

Logic outside that module implements the registers and address
decoding.  The address is used as a mux select; the mux inputs are all
of the register and the mux output always drives the I2C slave's
master-read data input.  The address is also decoded and when the
WriteDataValid strobe is active, the contents of the I2C slave's
master write output port are stored in an appropriate register.

It's also synchronous with a convenient clock.  It took about a day to
write, and I spent another day on a behavioral I2C master model and a
test bench.

No, I cannot give you the code, but I would imagine you've got enough
hints to complete your design.


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