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State Machine Coding?

Hello, I am writing a character controller using Altera MAXII device. This controller will monitor the input signals from lpt port. I make a simulation and download to real chip to verify function, but unfortunately it won't work as I designed. The simulation show that the state translate signals was initiated abnormal.. I pass this to Altera local FAE, no one knows why, and their "my support", no response. I also make the simulaiton on their QII 4.1 and 4.2, the result is the same. Since I can't post my code and result here. If you are interested, I can mail to you for your reference!

Thank you in advance.

BR, Johnson

Reply to
Johnson Lee
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It won't work as you *expected*.

If the simulation doesn't work, there is a design error. Debug it.

-- Mike Treseler

Reply to
Mike Treseler

Well, My simulation is ok! But the result is not as what I planned to have. I abstracted some codes and attached in below for your reference:

--------------------------------------------------------------------- PROCESS( RST, FLAG2, TP41, TP11, TP51, TP31) BEGIN IF RST='1' THEN BIOS1_ck

Reply to
Johnson Lee

Check out this CPLD tool

formatting link

CPLD0100-00 MAINBOARD FACT

  • Quick affirmation of a logical design
  • Affordable system
  • Free upgrades over internet
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  • LAB board on PCB for own experiments
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  • 64 channel pre connected scanner for all I/O of the ATF1508
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This should allow you to single step your PLD at 1 Hz or less , while feeding it with stimuli form your PC. It will record what is happening and can store the output values back on the PC.

Cost of the board is about $600 + VAT.

Built to work with the Atmel CPLDs. If you wan tto try with others, you have to find out a way to adapt.

--
Best Regards,
Ulf Samuelsson
ulf@a-t-m-e-l.com
This message is intended to be my own personal view and it
may or may not be shared by my employer Atmel Nordic AB
Reply to
Ulf Samuelsson

Consider a synchronous design.

-- Mike Treseler

Reply to
Mike Treseler

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