I'm using an Altera ACEX1K and can't find the condition of the IO-Pins during configuration and initialisation of the FPGA ??? Can there be an input on the IO-Pins during configuration and initialisation ??? Especially can there be a clock on GCLK0-Pin during configuration and initialisation ??? Thanks, Manfred
I've had running clocks on a 10KE during configuration without hassle. The ACEX is very similar as I understand it.
Cheers, Martin
-- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conekt
You shouldn't count on them being pulled up or pulled low.
Sure. You could have an smd clock oscillator on board and wouldn't want to unsolder it just for configuration.
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Yes, there can be inputs. The ACEX pins are weakly pulled high before and during initialization.
Yes, no problem.
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