DEV_CLRn and CRC_ERROR on ALTERA Cyclone

Dear everybody,

I have two dubious about using the DEV_CLRn and CRC_ERROR pins on ALTERA Cyclone.

If the DEV_CLRn pin is LOW during FPGA configuration, does the active configuration (AS) take place since the device's internal registers are cleared by DEV_CLRn ?

I would like to enable the CRC_ERROR feature but I don't know what to do when this pin goes active. Do I have to restart the configuration making a transition on CONFIGn ? Do you suggest something else ?

Best Regards

/Alessandro

Reply to
alessandro.strazzero
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The DEV_CLRn to the best of my knowlege has nothing at all to do with = the cofiguration mode Cyclone will be set to. The mode is set via the = mode select pins.

I don't know of any CRC_ERROR pins on the Cyclone either. CRC is, to = the best of knowledge, something that happens under the hood during = configuration, see below.

Cyclic redundancy code (CRC) circuitry validates each data frame (i.e.,

sequence of data bits) as it is loaded into the target device. If the = CRC

generated by the device does not match the data stored in the data = stream,

the configuration process is halted, and the nSTATUS pin is pulled and

held low to indicate an error condition. CRC circuitry ensures that = noisy

systems will not cause errors that yield an incorrect or incomplete

configuration.

Take care,

Rob

Reply to
Rob

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