Dear everybody,
I have two dubious about using the DEV_CLRn and CRC_ERROR pins on ALTERA Cyclone.
If the DEV_CLRn pin is LOW during FPGA configuration, does the active configuration (AS) take place since the device's internal registers are cleared by DEV_CLRn ?
I would like to enable the CRC_ERROR feature but I don't know what to do when this pin goes active. Do I have to restart the configuration making a transition on CONFIGn ? Do you suggest something else ?
Best Regards
/Alessandro