ACTEL ProAsic Plus

Not much info to go on......

I had no problems with the ProASIC+

except that the P&R is very slow,

Hans

1) If you are used to programming SRAM-based FPGA's, you may have gotten lazy about explicit resets for registers, as they tend to get implicitly initialized when the bitstream is loaded. In contrast, flash-based archictures are more likey to come up in an unusual state, and not necessarily just a random selection from the states you planned on having happen. So make sure everything has an explicit reset. 2) The actel tools, and synplify which they use, tend to be a bit pickier than xilinx or altera. For example, if you temporarly remove any dependence on an input signal it may get optomized out of the design, which is fine. What you don't expect is to find out that it's been optomized out of the pin assignments, such that when you un- comment-out the use of that signal, you now have logic depending on an un-assigned pin. 3) What I really hate though is the programmer's insistence on programming and then verifying the _unused_ bits. I don't usually have verification turned on during debug, and a programmer which doesn't give you a choice, plus is slow to start with...

So how fast/slow are these devices to pgm ?

-jg

Next time I have to do one I'll try to remember to time it. My gut impression is that the little APA100 takes siginificantly longer then the conflig flash for moderately large altera parts with a lot of complied in data tables.

I think my tossed-together embedded processor stub which a customized altera jam-player can control over a serial line to reconfigure a config flash in the field may go faster (its about 1/4 the speed of usb blaster) Actel has a presumably modified version of the altera jam player source code on their site (with attribution of course) and I'm thinking I may waste an afternoon on that and see if it isn't faster, given that I can probably force it not to verify.

About 3min for an APA300 with Flashpro Lite. Other programmers could be faster, never used Flashpro or Silicon Sculpture for APA.

bye Thomas

All adders are ripple carry, so timing is a big concern. Also read the data sheet carefully. Their JTAG interface has problems. You can actually powerup the device with the boundry scan logic enabled in an arbitrary state that can damage the device. It happen to me. I ended up with a 150 ohm resistor tied to TRST to ground to keep the JTAG in reset when not in use. Also with the Flash Pro, it took 5 mins to program a APA150.

Dave

This applies to other JTAG devices as well even very expensive space-qualified RT/RH Actel fpgas and microcontroller.

Also with the Flash Pro, it

My APA1000 takes 22 minutes to program (and verify programmed/non-programmed bits) using a parallel port FlashPro-lite programmer,

Hans