Hi group!
Please any one could provide answers to these:
1) Are the dedicated clock pins (GCLKx) of spartan2 [XC2S150, Vccint=2.5V and Vcco=3.3V]also 5V tolerant? If yes, then do we need to select LVTTL for these clock pins also?2) Can the Xilinx ISE tool meet all pin location constarints with
100%guarantee? or a failure may occur like in case of some other constraints? Is pin locking affected by some other constraints we might be using in the design?Regards Rider
Rider,
1) Answer 11313 which refers you to vtt002.pdf states that IO inputs are 5V tolerant for LVTTL or PCI standard inputs.2) Sorry that I can not answer the second question (not a tool guru). But I suspect that all constraints are not exclusive, and that they do interact.
Aust> Hi group!
I can't make any guarantees, but I have never seen problems routing Spartan2 devices, even with all pins locked. Most customers do lock down their pins before running place and route.
There are 2 areas I can think of that may interract. First would be if you try to use a global clock buffer inside the FPGA and don't constraint the input to the appropriate pin. Second would be if you have really tight timing constraints that are difficult, or impossible to meet based on where the IOs are located. In this case, the design usually routes, but may not meet timing.
Steve
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