Please any one could provide answers to these:1) Are the dedicated clock pins (GCLKx) of spartan2 [XC2S150, Vccint=2.5V and Vcco=3.3V]also 5V tolerant? If yes, then do we need to select LVTTL for these clock pins also?
2) Can the Xilinx ISE tool meet all pin location constarints with100%guarantee? or a failure may occur like in case of some other constraints? Is pin locking affected by some other constraints we might be using in the design?