Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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IC40HX PLL Simulation
I'm trying to get started with a design using a Lattice ICE40HX (done that before) but this time I'm using the PLL. My usual design flow (with Lattice ECP3 or XP2) is to use the Lattice IP generator...
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9 years ago
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What would you say is the best board to buy
Im looking at a hardware project which will be a DVB-CSA descrambler. Idea is a pci-e board with an FPGA, any body know of a nice development board that i can buy off the shelf, which will take in the...
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9 years ago
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Bypass Xilinx flexlm license check
Hello, While I certainly do not condone piracy, and I believe Xilinx should be com pensated for their hard work, sometimes it can be handy to run ISE without limitations on the range of targetable...
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9 years ago
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disadvantages of inferring latches
Hi all, I always hear from FPGA designers that latches are "dangerous" and that it' s very important avoiding them. I wonder what are the technical risks resul ting by using latches. As far as I...
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9 years ago
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CFP: Symposium on Architectures for Networking and Communications Systems (ANCS)
-------------------- CALL FOR PAPERS -------------------- The 11th ACM/IEEE Symposium on Architectures for Networking and Communicati ons Systems (ANCS 2015) May 7-8, 2015 Oakland, California, USA...
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9 years ago
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Thomas' Calculus Early Transcendentals, Single Variable (13th Edition) by Thomas, Weir & Hass
I have solutions manuals to all problems and exercises in these textbooks. To get one in an PDF format contact me at: kalvinmanual(at)gmail(dot)com .. replace (at) to @ , and (dot) to (.) and let me...
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9 years ago
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Program IO 1.2V
Hi, I would like to create a project with FPGA. You can imagine it as a debug board that need to communicate to other systems with defined protocols and standards... I would like to begin with a...
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9 years ago
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How to get optimized/correct PLA or SOP output from abc with selectable phase?
I can not seem to get a decently optimized .PLA file out of the abc I have: a blif of some combinatorial circuit. What I want: the SOPs for a single output bit as a .PLA file (or something equivalent...
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9 years ago
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Linux USB JTAG Cable Driver for Xilinx Impact
I've read much on this topic elsewhere, but I'm confused on some things, no t to mention some of what I've read is out of date w.r.t. s/w versions, etc . I've been frustrated on a previous attempt to...
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9 years ago
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bitstream support for Artix 7 in torc?
Does TORC provide bit stream generation for Artix 7 devices??? Looking at the torc source files, i see classes only for bistrem for Spartan and Virtex family. Can it be used for Artix device?? If not,...
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9 years ago
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practical experience with GPL IP core in commercial product
I was wondering if anybody has had practical experience using IP licensed with the GNU Public License (GPL, not LGPL) within a commercial FPGA development. I found some Verilog under GPL I would like...
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9 years ago
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Quartus II TCL or Command line
hi all, How can I add VHDL files to Quartus II project using TCL or command line??? Thank you,
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9 years ago
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The EDIF variant used by fit150X.exe
Can anyone point me to samples of the edif variant accepted by the atmel PLD fitters? Google can't seem to find any, and their free CUPL seems to generate .PLA things only.
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9 years ago
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MIPI M-PHY and FPGA?
Hi, does anybody know whether it is possible (or impossible) to use an FPGA's serial transceivers for a MIPI type 2 M-PHY link (i.e. 1.5 GBit/s)? Xlinx' book it look easy, but I suspect this gets very...
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9 years ago
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looking for dev kit for ProAsic3
Hi everyone, I'm looking for a dev kit for a ProAsic3 A3PE3000 (microsemi) with some minimum amount of functional blocks around (volatile/non-volatile memory, few peripherals like UART, USB, SPI ...)....
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9 years ago
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