Field-Programmable Gate Arrays

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[WTF] Hierarchical designs and ATMELs CPLD fitters

I've been playing with atmels old stuff again... I can not seem to get their fitter to accept hierarchical edif. I am u...
0 comments posted 11yrs
posted by klammerj
0 comments posted 11yrs posted by klammerj

another MicroZed project

Another board: https://dl.dropboxusercontent.com/u/53724080/PCBs/P350_12.jpg The microZed compute platform plugs into t...
0 comments posted 11yrs
posted by jlarkin
0 comments posted 11yrs posted by jlarkin

Transfering image file to DDR RAM using EDK

Hi, I am working on Xilinx Spartan 3e Starter kit board which has DDR Ram. I have to transfer image file to DDR and sto...
1 comments posted 11yrs
posted by rashmicbe
1 comments posted 11yrs posted by rashmicbe

Why two hold checks done byTimeQuest

Hi, TimeQuest says it uses two hold checks per each setup check. The first hold check for previous latch edge with curr...
0 comments posted 11yrs
posted by 37480
0 comments posted 11yrs posted by 37480

Vivado is intensely frustrating

So, the following ROM initialization code should be entirely synthesizable. Not so, according to the latest version of...
3 comments posted 11yrs
posted by rgaddi
3 comments posted 11yrs posted by rgaddi

Artix-7 tools, ISE vs Vivado

Hello, What are the practical pros and cons of using each of ISE or Vivado for the Artix-7 family? I am interested in t...
4 comments posted 11yrs
posted by vladitx
4 comments posted 11yrs posted by vladitx

Send a pulse across clocks

Hello, I want to send a pulse from one clock domain to another, knowing tha t from the time event that this pulse is ge...
14 comments posted 11yrs
posted by capossio.leonardo
14 comments posted 11yrs posted by capossio.leonardo

[RANT] XILINX, Are you freaking kidding me ?

So I wanted to know if it was possible to update an old embedded-developmen t kit license that's expired. There's nothi...
8 comments posted 11yrs
posted by google
8 comments posted 11yrs posted by google

Altera Cyclone II

Hi, I have a Altera Cyclone II design where I am looking for a good way to make a complete reset via HDL. In Xilinx the...
8 comments posted 11yrs
posted by michael_laajanen
8 comments posted 11yrs posted by michael_laajanen

[cross-post] nand flash bad blocks management

Hi everyone, We have ~128Mbit of configuration to be stored in a Flash device and for reasons related to qualification...
6 comments posted 11yrs
posted by al.basili
6 comments posted 11yrs posted by al.basili

Name this pipelining technique

Hi, I vaguely recall reading papers that described an automated pipelining technique that could take an existing synchr...
4 comments posted 11yrs
posted by allanherriman
4 comments posted 11yrs posted by allanherriman