MIPI M-PHY and FPGA?

M-PHY is not supported

Antti,

Sorry for digging out an old thread.

Why is it not supported? M-PHY is 8B10B coded and embeds clock? Is it the low-rates that the FPGA transceiver won't support or are there some "IDLE" states or somethings that the GTs can't handle.

Is it possible to "come up" in a high-rate and avoid the low-rates if this is the problem?

Thanks, M

FPGA's

away

--------------------------------------- Posted through

I've heard the same, that the low-rate mode is one problem. Don't think you can bring up the interface in HSx mode in a standardized way (product-specific "hacks" via some 3-wire interface etc could still work).

I wonder whether one could reconfigured the line drivers "on-the-fly" and drive the low speed mode from the FPGA fabric, bypassing the SERDES etc hardware blocks.

--------------------------------------- Posted through

the low-speed can be patched in if desired. for some reason I did think there are more complications ..

you

work).

and

Does M-PHY "turn-off" transmission and expect a fast wake-up time? The FPGA transceivers and related PLLs would take a while to come up (and would need to be reset afaik). Googling M-PHY gives a lot of mentions of sleep/hibernate but I can't find a good reference document...

I know DigRF3G (which is related to some extent I think) has requirements like this (at much lower rates, it doesn't need FPGA SERDES just LVDS).

--------------------------------------- Posted through

my understanding is that the "PLL power-up & stabilization time" is implementation dependent. The master continues in HS mode by sending SYNC symbols, then "start-of-frame". The SYNC does what its name promises, so maybe there is no need to be fast.

That said, I wouldn't bet too much money on this superficial analysis. And yes, the low speed mode is probably not the only problem...

--------------------------------------- Posted through