Why are there no low pin count FPGAs?

The smaller parts are called CPLD's. They start at 20 pins or so.

John

Yeah, but what if you want lots of logic and very few IO pins?

Cheers Terry

John Larkin schrieb:

But there also are no "larger" CPLDs in small packages...

I would have needed them several times. For example, the smallest package for the Xilinx 95144XL is the TQFP100 (with 0.5mm pitch :-( ) - I would like that chip in a 44-pin package for applications with less I/O.

The dilemma is, there simply are no such larger programmable logic devices (no matter if CPLD or FPGA) in small packages (from neither maker). Seems there's not much market to them, or they didn't recognize there is one...

--
Dipl.-Ing. Tilmann Reh
http://www.autometer.de - Elektronik nach Maß.

Most customers want lots of I/O, the market for smaller packages would be limited and they would be very expensive.

Leon

Well your problem here is lots of logic. Lots of logic = large silicon area. Large silicon area = large package. Manufacturers are not going to produce a

18 x 18mm package - or larger - with 20 pins! It is just uneconomic to do so.

If you have a minimal logic requirement go for a CPLD, packages typically will have fewer pins.

Slurp

Consider this, is it easier to not use a pin rather than trying to add a pin for a customer that needs it? FPGA capabilities is a compromise. Otherwise people would just had an asic made. So it makes more business sense to have one chip sold to those that needs many pins and those that doesn't need them. Split the production, and cost rises. The only argument I can see is that of not useing bga packaging. And too thin pitch that is just unsolderable by any normal means. And one could always make a small breakoutboard vq100->dil14 etc.. if one wants that.

Or the chips are huge and _need_ those big packages.

Although I'm always willing to believe in vendor stupidity.

--

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If you're just talking about board real estate, then with the little teeny tiny pins on those little flat packages, the whole thing is about the size of a postage stamp. Just lay out your board with the .5mm traces or whatever, and strap the unused pins to Vcc or gnd. IOW, figure out the mounting, and just ignore the pins you don't need. Then the only problem is the PCB layout.

Good Luck! Rich

That's probably less common than the reverse, running out of pins. My designs seem more often constrained by pin count than by internal resources, unless we bite the bullet and go BGA.

John

Virtex 2 has small BGA packages with 0.8mm pin pitch. There are web sites discussing how to solder BGA packages at home using a toaster oven. Many designs require large amounts of I/O. Thus, the FPGA manufacturers cater to the average. Plus, a large percentage of pins are power/ground.

--
Mark

That seems to be what I was missing. As discussed in this topic by others though - these seem to be much more limited in features.

So that brings me to a new question: Are there any FPGA/CPLD like devices that have built in ADCs? That is the only feature of importance I'd be losing by switching over to a CPLD from a microcontroller. Does such a thing exist? The board that this is intended for is very small (1.5x4.725cm) and very full so having to add an external ADC would be difficult.

-Mike

You might check Actel. You can also make a single-slope or delta-sigma ADC using mostly internal FPGA resources, if accuracy needs are moderate. There are also tiny ADCs around, SOT-23 and smaller.

John

You are right, all FPGA's have HUGE pin counts. The higher the logic density the greater the pin count. It is one of my pet hates. For one of our applications we needed one of the top of the line FPGA's for the density, but only needed about a dozen I/O pins. So we were forced to use a *960* pin BGA - INSANE!

We asked the top three FPGA manufacturers to explain this, and their general response was that it doesn't really cost them any more to put on all the extra I/O, and there is most demand for the high pin count, so they have simply abandoned the low pin count market for good. If I recall correctly, Actel were the only ones who put their hand on their heart and said they would continue to support the "low-ish" pin count QFP packages.

Dave :)

Wow, what sort of application needs all those gates but only a dozen i/o's?

John

Counters.

Cool. If we use SPI to manage and read out the counters, that leaves 9 count-input pins. So you can have nine, say, 10,000 bit counters.

John

It was a dual path redundant E1 data stream over 155Mbit ATM fibre. So basically, just 6 serial buses in and out - a dozen pins total plus a few misc.

The commercial E1 and ATM VHDL cores we had took up lots of resources, so we needed the biggest device Altera had at the time, and of course that only came in a 960pin BGA :-(

Makes quick prototyping a ridiculous exercise!

Dave :)

"M. Noone" schrieb im Newsbeitrag news: snipped-for-privacy@h76g2000cwa.googlegroups.com...

We produce small FPGA and CPLD boards in a PAL compatible 24pin DIL pinout. The FPGA board also incorporates 512kx8 SRAM and 8Mx1 FLASH. It's well suited for education purposes and serial I/O.

see:

However lots of customers asks for more I/O's...

So the next ones have more I/O's, for $++.

MIKE

PS: ROHS forces us to sell out our PB contaminated modules, so its prices are very userfiendly...

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !

A 40 pin DIL option would be nice, also maybe a basic lower-cost version without flash, sram and level-shifters.