I need a FIFO, with an 8 bit input, and a 32 bit output (one output is read for every four inputs). The inputs will arrive at 25 MHz. The input and output clocks are asynchronous. I would like it at least 256 bytes deep, but more is better.
A co-worker suggested that I just line up four 8-bit FIFOs and multiplex the input clocks. But I would rather have a one-chip solution, rather than 4 FIFO chips plus the multiplexer circuit.
Another co-worker suggested an FPGA, but I have never done that before (although I have played around with a Verilog simulator), and don't know if it can be done cheap enough (I would like to keep the cost under $10). Besides, I have heard that FPGA's are current hogs.
If anyone has any good ideas, please let me know.