2 leg crystal on FPGA: Lattice vs Xilinx

Virtex4 actually has this. It isn't well documented, but it is there. Xilinx uses it for the NBTI fix in V4 devices. It does have an internal purpose, I think it was for one of the configuration download modes.

I don't recall off-hand the magic incantation to use it, I'd have to find it in my design files. I think you have to make a hard macro in FPGA editor to get at it.

yes PMV primitive can be used as free running clock, but its tricky to use it as it xilinx undocumented feature

Antti

I can't address the specific chip, and you have to think about input->output delay, but it shouldn't be a big problem. I did just this on a recent design using a Xilinx 5V CPLD, and it worked beautifully with a 10 MHz crystal. I used no parallel resistor, and no series resistor, although I was just a little worried about overdrive, there. My caps were 15 pF (xtal vendor recommended 18 pF, but I have some parasitic capacitance on the board and chip pins). As far as I can tell it is working like a dream.

You might set the slew to slow, that is still plenty fast for a 25 MHz signal.

Jon

Don't bug Xilinx with such troubles. If the oscillator doesn't work reliably, go back to your OWN bench and figure out what you need to do. With a series and parallel resistor and resonating caps, you should be able to find component values that make it work.

Now, maybe a volatile-config FPGA is a different sort of problem, because the power comes up and stabilizes long before the internal logic finishes configuration and becomes active. This may allow the power-on transients to have died out so the parallel resistor is critical to balance the input right on the threshold, or the start-up is not reliable. I think the Xilinx CPLDs work the same way, just that the internal configuration happens much quicker.

I have been using Xilinx CPLDs and smaller FPGAs in places others often select microcontrollers, because latency is much less, and I feel the programming has fewer pitfalls. Of course, as long as you are not using a uP core, the application limits which technology is appropriate.

Jon

well, its not "might" in some cases you "need" set slew slow (or maybe further adjust the component values) with slew-fast on S3A there was overdrive overkilling the oscillation so it periodically stopped and started again (the inverter output only, the input was always seeing the crystal swing), but the DC bias did run away into outside the input range so the internal signal did stop.

well, maybe have to use "safe ring oscillator" to bootstrap and monitor the crystal circuit and DCM locks but I think with extreme care and bench testing it should be all doable

Antti

Antti, you are correct, but so also is Peter.

Whilst this is common in the Microcontroller space, it is black magic to the FPGA guys. Also remember, they are working fabless, and are far more focused on MHz and mA, than on Osc details. They do not want, (or need) the hassle/delays, of talking with their Fab partners, and characterising an OSC block

- that then may not work, or give poor Phase performance.

-jg

One litmus test for Xtal Osc circuits, is to remove the Xtal.

If it stops oscillating that is a good sign! :)

If it does not stop oscillating (above), what you actually have, is a crystal locked oscillator - and yes, you CAN make those (have made a few here ) but they are VERY sensistive to process/part changes.

So you really have to have a good reason to go down that path.

NXP show a LVC2GU04, for 9.7c, so why not just use one of those ?

The 74AUP1Z04 includes a bias-resistor, and is more purpose built, for ~12.6c - it also gives faster output edges. [Only minus, is no injection current control]

Or, I see 1GU04/1G14 are close to 3.9c now, so if you can tolerate two tiny packages, you can control the injection current on the

1GU04, and work over a very wide frequency range.

-jg

1-0 for Lattice then: MachXO (biggest 2 devices) has an on-board osc, and ECP2, and ECP2M and XP2.

Fairly easy to use even.

Luc

You can build Ring osc in almost any Prog Logic device. We have done them in Atmel CPLDs, using foldback nodes, which avoids using a more valuable Macrocell.

Crystal Osc with Schmitt pins are fragile at best, but LC osc work quite well - so if you need a precision better than a Ring Osc, but not as high as a Crystal, then LC is usable.

SOT23 Digital Osc continue to advance, and tiny uC get better all the time in their analog-osc performance, so those are also OSC candidates

-jg