HDB3 - clock recovery????

Im designing Jitter Measurer for 2Mbit (HDB3) signal. Input signal must be decoded from HDB3 to recover clock signal. Is there any easy (or little bit hard) way to decode it (with error correction)????

I was thinking about putting hdb3 signal into serial-in parallel-out shift register clocked with 11,12,13 * 2Mbit. Analizing Parallel out of this register will enforce

11-13 multiply. Maybe you know/see any easier solution?? Maybe sb seen anywhere in net some good publications about jitter measurment??

Thx for help Greetings from Poland

5hinka
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5hinka
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There are chips on the market for decoding HDB3 such as the MV1442 from Zarlink. HDB3 was not designed for error correction. The decoder circuit has to remove the "B00V" code sequences (B=Binary (0 or 1); V= Violation)which have been encoded at the far end and replaces them with "0000". The "B" is introduced, as required, to keep the violations alternating in polarity. Error detection takes place by looking for other violations of the normally alternating Pos Neg pulse sequence which will cause a double violation of the same polarity. This may occur due to an extra "1" being changed from a "0" in the code - remove?? or a "0" being changed from a "1" - producing a violation in an adjacent bit position - can't remove. How do you find out which type it is?? Hope this helps Tony

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Tony Thomas

My mistake. I DO NOT need to decoder HDB3. I NEED to RECOVER clock. All chips i found decode hdb3. :-(((

Greetings

5hinka
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5hinka

The MV1442 does provide clock recovery using an external 16.384MHz clock if you are operating at 1.5 or 2MBit/s. See the following link

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You don't say what speed you want - is this not suitable? The conventional way of recovering clock is to feed the recovered data stream (not the one which has been HDB3 decoded, but the combination "OR" of the positive and negative input data) and stick it into a low Q tuned circuit. Amplify the resulting sine wave and square off. The second stage in the process is to feed into a narrow band phase locked loop in order to generate a highly stable clock which will then allow you to do jitter measurements. Best Wishes Tony

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Tony Thomas

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