How to build a phase detector?? I know that normal design is two flip-fops and NAND gate but it works only with phase difference between signals smaler than 1 (T). How could I possibly build a phase detector when phase difference between signals is up to 10-20 (T)?? It could be hole digital or digital/analog solution. Anybody know any suitable links?? Greetings
5hinka
Are you saying you have jitter that is up to 10-20*T?
How could you ever define that as "phase-locked"?
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et |
(a) divide both signals by N and use a 3-state phase detector. (b) make an extended state phase detector.
Both of these methods are detailed in "Phase-Locked Loop Circuit Design" by Dan Wolaver, Prentice-Hall 1991.
-- Tim Wescott Wescott Design Services
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IEEE is saying that jitter in 2Mbit signal (HDB3) can have jitter up to at least 5 T is jitter 10-20*T isnt very big. Greetings
I think you should be surfing for "Clock Extraction".
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et |
FM transmitters that use phase-locked signal generation can have phase-locked loops with this much phase difference.
NRZ digital signals that have gone through a number of repeaters can have short-term jitter that is this severe.
You define it as "phase-locked" if the average phase and frequency of the locked and input signals match, and if your phase detector never actually looses track.
See the reference in my other thread. I took the class from the author, he really knows what he's talking about.
-- Tim Wescott Wescott Design Services
Classic phase detectors fail on NRZ, but there are a variety of methods to extract a clock from such messes.
...Jim Thompson
-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et |
-- snip --
Minor detail. Actually if you have data that "jitters" by 10-20T then you probably need to have a fast clock extraction loop that gives you a nice clean digital clock followed by a clock regeneration loop that can stand the huge phase difference, because all the edge detection schemes are digital, and all the clock extraction schemes have some very analog properties.
-- Tim Wescott Wescott Design Services
Im building jitter measurer for 2MBit signal.
-------------- | estimating | | clock | -------------- | | ---------- | | -------------
-IN--|Extract. |------ ---------| Phase | |clock |----------------------------| detector | ---------- ------------
Estimating clock will be in different time periods. I have already Extracted clock from 2MBit HDB3 signal. I think that i will estimate clock on PLL changing FPD filter for different time periods.
The hole problem now is to build Phase detector for such big jitter.
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different
Simple. Use a 4 bit counter for incomming clock and local VCO. So the compare frequency is then 1/16. With the normal Phase detector with a working range of one period (T), you have a 16 T working range on the desired frequency.
Regards Falk
The huge jitter only occurs at low frequencies.
Firstly, let's fix the terminology. Your 'T' is more commonly referred to as a Unit Interval (UI) when measuring jitter on a 2Mbit/s circuit.
According to ITU-T G.823 (and a few others), the maximum tolerable jitter on an E1 is 1.5UIp-p in the band 20Hz - 2400Hz, and 0.2UIp-p in the band 18kHz - 100kHz. Other specs indicate that the jitter / wander may be as high as 18us p-p (36.8UIp-p) in the band from (1/1 day) to 0.8138Hz. (If you draw this on a graph, there's a nice
-20dB/decade slope between the segments.)
Since you are making test equipment, you should be able to generate and measure jitter with a higher amplitude than this, say by at least
6dB. Your 10-20 UI figure sounds reasonable, but only at mid frequencies.I suggest that a more reasonable specification for test equipment would be: > 80 UIp-p, for frequencies up to 0.81Hz > 3 UIp-p, for frequencies between 20Hz and 18kHz > 0.4 UIp-p, for frequencies greater than 18kHz.
I assume you are tracking the incoming phase with a PLL. If the PLL has a loop bandwidth of > 1.5 * 18kHz, the phase detector inside the PLL will never see a phase difference of more than 2 UI p-p, which means that a standard phase detector can be used without going outside its linear range.
Regards, Allan.
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