Hello
my question is rather general - does an Ethernet PHY chip require any additional initialization upon hardware reset or it is always platform specific? I'm asking this because I'm having a problem reading/writing registers of PHY chip from my code; the chip is wired to a ethernet SoC via S3MII bus. I just try to understand: am I missing something more fundamental or should go through the SoC datasheet ince again.
Thanks.
You are using the management lines of the interface, not the RX/TX lines?
The PHY will default to an address (0-31) on the management interface. The default address depends on the PHY and the way it's wired on the board (pull up and down). Check the PHY datasheet (or try all addresses).
Op Wed, 24 Feb 2010 08:46:18 +0100 schreef Mark :
Usually a software reset is performed to make sure that the Phy is in a sane state.
Another useful read is the IEEE Std 802.3-2005, part 3; more specifically section 2, chapters 22 and 28.
Yes and No.
The S3MII interface must work; if it is not working, it is an indication of a problem.
Vladimir Vassilevsky DSP and Mixed Signal Design Consultant
hey, i am having same sort of a problem .
i am using spartan 3E FPGA board with LAN83C185 PHY. I want to make 100Base Tx connection but i dont know what's wrong here. I have written the initialization code but i can't read or write to PHY . The code simulates perfectly but when i burn the code on FPGA, it doesn't work..
kindly help me out.
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