I working with an LCD display using this chip which is apparently function compatible with the ubiquitous HD44780 LCD controller. The initialization sequence is a set of commands because no one trusts the internal power up r eset. Rather than an MCU this will be driven from an FPGA with a repeating sequence, so I'd like to eliminate anything that is not important in the c ommands. In particular the "magical reset sequence" includes the Clear Dis play command which takes 1.52 ms to complete while the other instructions m ostly complete in 37 us (give or take as I mention below).
I'm wondering if this command is strictly needed. It clears the display da ta RAM, resets the data RAM pointer and resets some cursor functions. I wo n't be using the cursor and I can manually reset the data RAM pointer easil y enough. The data is completely written on a periodic basis, so clearing the memory is not useful. Does anyone know if this command does anything e lse that might be important? Or can I replace this command with one to sim ply set the display data RAM address pointer without impacting the operatio n of the display?
Does anyone know how many times the Function Set command needs to be sent t o be sure of starting the chip off right? The data sheet I have shows twic e for an 8 bit bus. I've seen people say three times for an 8 bit bus and4 times for a 4 bit bus.
Then there is the timing... There is a read register which returns a BUSY bit. This won't be used to simplify the circuitry, instead fixed times wil l be used. The data sheets talk about times given a 270 kHz clock which se ems to be generated internally. I'm unclear on how much margin I would nee d to include or if that is already included. Oddly enough the data sheet t alks about using a resistor when "crystal oscillation is performed", but I' m pretty sure they are talking about an internal RC oscillator. I found on e web site that talks about this discussing the impact of Vcc and just plai n chip variations. The author speculates this is the issue that causes som e code libraries to fail.
I don't need to worry about the bus timing. I'm going to make the bus cycl e as long as the minimum instruction processing delay. Then it won't even be remotely close to the minimum timing specs.
I would fire this to measure, but I don't currently have hardware and need to construct a test bench to test my code. Knowing the actual requirements will help a lot.