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nee

Yeah I also calculated 3 wait states. Is it 3 wait states per machine cycle or one wait state/MC(machine cycle)?.

I have inserted one wait state during opcode fetch MC, one wait state while getting Higher byte address fetch MC & one wait state while getting lower byte address. Can you clarify my doubt? How many machine cycles totally would it take to read from ROM? I feel it need 3 Machine cycles to access data from ROM Suppose my processor has (A0-A15)16bit address bus.

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RIYA
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Perhaps you should try getting a real newsreader and a real Usenet account - that way you can reply to posts with proper threading and proper quotations, so that people can figure out what you are talking about! It's a lot easier to get help that way.

I think even Google's Usenet interface is better than

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David Brown

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