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synthesizeble Wait Statement in Procedure

Hy all,

I have a little problem to write a kind of WAIT-Procedure in VHDL. ( like in C, "loop until i = 0,...") This is necessary to pass some data to an external chip (Cypress SL811) to the right time.

In the end it should look like this: send_data(xyz); wait(t); send_data(xyz); wait(t); send_data(xyz); wait(t); ....

I know that I can do it in an process with a counter, but I would prefer a procedure, which I will put into the package body, and then call it when I needed. Has anyone of you gurus :-) an idea how to manage this?

Thank you very much, Roman

Reply to
Roman
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I am pretty sure this is not synthesizable. If you want something that can be synthesized, think about how you would build the circuit out of hardware and then describe that circuit using logic and clocked processes. You can put the logic inside a procedure. But you might do better to use a module and pass it a trigger signal.

--

Rick "rickman" Collins

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Reply to
rickman

This sounds like a use for a state machine.

-- glen

Reply to
glen herrmannsfeldt

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