can anyone explain me to calculate the wait states needed? Suppose we are using 120 nanosecond ROMs, which have valid data on the bus
120 ns after the falling edge on the Output Enable line with a clock rate of 25 MHz (which means a clock cycle of 40 nanoseconds). How many wait states must the microprocessor insert into each bus cycle that reads from the ROM?--------------------------------------- This message was sent using the comp.arch.embedded web interface on