5 years ago
The frequency is 440Hz, as expected, but the output duty cycle is not 50% a
nymore. The low level goes from counter=0 to counter=32767 (when bit 15
of counter is low) and then high level from 32768 to 56817. That gives us
"speaker" being high only 42% of the time. The easiest way to get a 50% dut
y cycle is to add a stage that divides the output by 2. So first we divide
by 28409 (instead of 56818) and then by 2. ????
I do not understand why we need to divide by 2.
Could anyone explain the above reasoning in more laymen way ?