Hi Jim,
Whats happening is that its sending the right data for the first 16 clock cycles...
Then its not stopping...
It send all 0's
Again the right data...
So somehow the spi0dat reg is receiving the info repeatedly....
I have tried using delays between the bytes
I have also tried with just one byte for 8 clock cycles...
Same error...
It is due to SW....but i dont see wats wrong with the SW....
thanks, Methi Jim Granville wrote: