SPI between several 8051s

I don't have the Silabs datasheet in front of me but I am fairly certain that so long as you have one master and several slaves, no rewiring is needed.

This is a special to Silabs question and not really an SPI question. In the very distant past I came up with a sort of a "party line" interface. If you have multiple masters, it could be an idea worth looking at. The basic idea was to use a switch like a HC4053 to flip the connections back and forth as needed.

How are you going to do the selects? MOSI is (obviously) the master out. If a device thinks it's the master it's going to want to talk on MOSI.

That depends on the 8051. Does it even do SPI slave? Read the datasheet.

Why not use the UART and make a ring network?

I am adding SPI RAM to an existing system anyway so I figured SPI communication between processors would make sense.

Thanks!

t. =A0If

heet.

The data sheet says that the SPI port can be configured as both master and slave. Its SPI chip select is an input that initiates SPI its own slave mode unless it being used as an output during a master mode operation.

That may be less easy than you expect. SPI can be pretty fast and there is no handshake from the slave; if it is a processor you will have to just wait the maximum latency time for every byte you send. And that is the easier part. The master has no way of knowing whether the slave has sent a byte or not, nor does it have a passive way of knowing whether the slave has a byte ready. Many years ago I did that (one SPI master many slaves) and solved this by sacrificing one bit every byte for that purpose. Works fine - but in my case 1 mS latency was OK and so was

Dimiter

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I did SPI interface between two AVRs; slave AVR was used as I/O extension and as a host for reflashing of the master. That was before AVRs with self programming capabilities.

In addition to the problem you mentioned, there was other hurdle: there is no way to know on the slave if there is an ongoing SPI transfer from master. I had to add separate lines for handshaking in both directions; with rather complicated protocol.

Amen to that. Especially if the slave needs to generate asynchronous requests to master.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

The master needs a select for every slave. How are you planning to wire this so master and slave are wired the same? As much as I dislike I2C, it may be a better choice in this application.

This must have been platform specific, I did not have it on the hc11. I just had to sacrifice a bit so the host would know whether the byte the slave shifts out is output from the slave or just the last byte which it got in. So the host was sending bytes with bit 7 always set while the slave was sending bytes with bit 7 always clear (or was it the other way around). That was good enough, I needed no more wires.

The bus would allow that (SPI was just a tiny part of it for configuration purposes), but over SPI only polling was the only option, obviously. Which was done anyway, BTW :-).

Dimiter

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The UART can be used as a "party line" rather than a ring.

The micros know that a byte is intended for them if you address them using the 9 bit mode. The interrupt is only generated on a match.

I think that the Silabs parts offer a little help on that issue.

The SPIxxCFG or SPIxxCN register has an indication that a transaction is going on (IIRC)