Voltage multiplier

Well, the issue is how to "drive" it.

Hey, this doesn't look entirely stupid:

ftp://jjlarkin.lmi.net/Digital_Power.JPG

It gives us a few discrete choices of photodiode voltage, good enough. The FPGA can tweak the flyback frequency and duty cycle as required.

John

With your original oscillator, I thought. (Sinewave, because cleanliness is next to Godliness.)

That works fine. A little switchy / rippley, but nothing a Phil- terplier wouldn't quash. I thought you didn't want flyback, but, if you don't mind it, Bob's yer uncle.

-- Cheers, James Arthur

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Your circuit wasn't running as a Baxandall oscillator when I simulated it. The drain of M1 was swinging through about 30V, but the drain of M2 sat at about 13V with only a couple of volts of swing.

Not the MOSFET version. But it doens't look as if you have either.

The real initial condition is equal current through both sides of the centre-tapped winding and no net flux in the transformer core. Neither MOSFET is "on" until the voltage at the centre-tap has risen high enough - 2V typical, 1 to 2.5V worst case - to turn one of the transistors on. In practice, one will turn on before the other, and provide enough asymmetry to give you instant start-up, which doesn't happen with LTSpice's identical 2N7002's. The current through L3 then ramps up, mostly charging C1 in the first instance, but as C1 charges to towards 47V, progressively more of the curren will be diverted into L1 or L2 (but not both) and the voltage at the centre-tap will rise towards 23.5V. Once the centre tap has risen above 15V, the current through L3 stops rising and starts falling, and your oscillator has been set up in about a quarter of a cycle.

The unrealistic bit is the perfectly matched 2N7002's. The cherry- picked intial conditions are a quick and dirty way of getting around that.

True.

Only if M1 and M2 are very closely matched.

You seem to be putting too much faith in the LTSpice simulation. What does a real circuit do?

It would be - if the initial surge current were real, which strikes me as highly unlikely.

-- Bil Sloman, Nijmegen

Yes, a sinewave supply is very appealing.

This circuit is too nice to abandon on some point of principle. A biggish gate resistor can slow down the fet enough to tame switching spikes, efficiency be damned.

Our tendency lately is to push uncertainty into FPGAs, where things can be tweaked without cutting and soldering.

It took me all weekend to get it that simple. I'll breadboard it with parts we have, just for fun.

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What's the FET at the output for? (If you don't mind a stupid question.)

George H.

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The LND150? That's a Supertex SOT-23 depletion-mode nfet. It's a current limiter, 1 mA or so. Noise filters a bit, too. (Should be an LND250, actually.)

This needs a current limit, since there's a straight-through path from

+12 to the output.

John

You didn't simplify it, you swept all the cruft under the FPGA rug. ;) Hope nothing too sensitive is hanging on the +12!

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net

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75% west of the LND150 should be easy. If you ditch the zeners and add a feedback loop the FPGA can even regulate the output, maintaining the efficiency.

You might even (depending on your other needs) be able to stop the switcher completely during critical operations, eliminating switching noise. Or, you could synchronize switching transitions so they happen when it doesn't matter. All depends on your parameters, natch.

I did that with a synthesized transmitter once upon a time--boost SMPS, out-of-phase, but synchronous with the PLL, to reduce phase noise in the synthesizer.

-- Cheers, James Arthur

I don't care much about efficiency here. The sihnal is, roughly, 200 ns flashes of UV every 20 us or so. Average photodiode current is probably 10s of uA.

That is feasible. The FPGA can do all sorts of stuff, like vary the switcher duty cycle as a function of what output voltage we've selected.

Digital Power!

John

You say that like it's a bad thing!

Well, maybe I could add a little filtering here and there.

John

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[snip]

It's NOT a stupid question... I await with amusement for what Larkin will claim (after he consults Bill SLowman ;-) ...Jim Thompson

--
                  [On the Road, in New York]

| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |
             
I love to cook with wine.     Sometimes I even put it in the food.

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This senile old hen has nothing to say about electronics any more. He just cackles.

And it seems he doesn't know about depletion fets, and can't use google to find out.

Sad.

John

On Sep 26, 6:28=A0pm, Bill Sloman wrote:

Ferrites certainly didn't work, and reducing R6 and R7 much below 1k didn't help either - the transistors M1 and M2 wouldn't saturate. On the other hand, fiddling with R6 and R7 didn't seem to make much difference to the start-up.

When I had the time to run a simulation, that proposition turned out to be wrong. Even with deliberately different threshold voltages (by

10mV) in the two MOSFETs, the oscillation took some 400usec to get going, and the supply current went up to a peak close to an amp, exactly as you said.

Another thing I thought I knew that wasn't so.

A 2msec ramp pulled it back to 526mA peak - albeit with a pretty narrow peak - and 3msec to 431mA. Ramping it more slowly still didn't win much. Since the running current drawn peaks at 270mA and averages to about 80mA DC, a narrow - about 85usec - 530mA peak ought to be tolerable. You'd presumably need some filtering to keep the roughly

400mA peak-to-peak regular ripple out of the rest of the circuit.

Version 4 SHEET 1 2008 1264 WIRE 128 16 -320 16 WIRE 256 16 208 16 WIRE -320 64 -320 16 WIRE 128 128 96 128 WIRE 256 128 256 16 WIRE 256 128 208 128 WIRE 320 128 256 128 WIRE 432 128 400 128 WIRE -320 176 -320 144 WIRE 96 192 96 128 WIRE 224 192 96 192 WIRE 432 192 432 128 WIRE 432 192 288 192 WIRE 512 192 432 192 WIRE 704 192 592 192 WIRE 832 192 768 192 WIRE 864 192 832 192 WIRE 976 192 928 192 WIRE 1104 192 976 192 WIRE 1104 224 1104 192 WIRE 96 240 96 192 WIRE 832 240 832 192 WIRE 976 240 976 192 WIRE 432 272 432 192 WIRE 96 336 96 240 WIRE 512 336 96 336 WIRE 832 336 832 304 WIRE 832 336 592 336 WIRE 976 368 976 304 WIRE 1104 368 1104 304 WIRE 96 416 96 336 WIRE 144 416 96 416 WIRE 256 416 224 416 WIRE 304 416 288 416 WIRE 432 416 432 272 WIRE 432 416 384 416 WIRE 96 464 96 416 WIRE 432 464 432 416 WIRE 288 496 288 416 WIRE 288 496 208 496 WIRE 176 544 144 544 WIRE 208 544 208 496 WIRE 208 544 176 544 WIRE 256 544 256 416 WIRE 336 544 256 544 WIRE 384 544 336 544 WIRE 96 608 96 560 WIRE 208 608 208 544 WIRE 256 608 256 544 WIRE 432 608 432 560 WIRE 208 752 208 688 WIRE 256 752 256 688 FLAG 96 608 0 FLAG 432 608 0 FLAG -320 176 0 FLAG 208 752 0 FLAG 256 752 0 FLAG 976 368 0 FLAG 1104 368 0 FLAG 96 240 n003 FLAG 432 272 n004 FLAG 256 16 n002 FLAG 336 544 n007 FLAG 176 544 n008 SYMBOL ind2 112 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 33=B5 SYMBOL ind2 304 144 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 33=B5 SYMBOL ind 112 32 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L3 SYMATTR Value 130=B5 SYMBOL nmos 384 464 R0 WINDOW 0 133 16 Left 2 WINDOW 3 109 51 Left 2 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL cap 288 176 R90 WINDOW 0 72 35 VBottom 2 WINDOW 3 79 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 330n SYMBOL res 240 400 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 3K SYMBOL res 400 400 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 3K SYMBOL voltage -320 48 R0 WINDOW 0 64 35 Left 2 WINDOW 3 64 71 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value PULSE(0 15 0 2m 1m 50m) SYMBOL res 240 592 R0 WINDOW 0 64 58 Left 2 WINDOW 3 62 95 Left 2 SYMATTR InstName R3 SYMATTR Value 1K SYMBOL res 192 592 R0 WINDOW 0 -65 57 Left 2 WINDOW 3 -69 94 Left 2 SYMATTR InstName R4 SYMATTR Value 1K SYMBOL cap 768 176 R90 WINDOW 0 -50 32 VBottom 2 WINDOW 3 -40 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 330n SYMBOL cap 992 304 R180 WINDOW 0 -49 44 Left 2 WINDOW 3 -45 7 Left 2 SYMATTR InstName C3 SYMATTR Value 1 SYMBOL diode 848 304 R180 WINDOW 0 72 52 Left 2 WINDOW 3 53 13 Left 2 SYMATTR InstName D1 SYMATTR Value GSD2004W-V SYMBOL diode 864 208 R270 WINDOW 0 84 18 VTop 2 WINDOW 3 70 30 VBottom 2 SYMATTR InstName D2 SYMATTR Value GSD2004W-V SYMBOL res 1088 208 R0 WINDOW 0 67 53 Left 2 WINDOW 3 59 88 Left 2 SYMATTR InstName R5 SYMATTR Value 100K SYMBOL nmos 144 464 M0 SYMATTR InstName M2 SYMATTR Value 2N7002A SYMBOL res 608 176 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res 608 320 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1k TEXT 288 48 Left 2 !K1 L1 L2 1 TEXT -88 200 Left 2 !.tran 20m TEXT -480 840 Left 2 !.model 2N7002A VDMOS(Rg=3D3 Vto=3D1.61 Rd=3D0 Rs=3D.7=

5 Rb=3D.14 Kp=3D.17 mtriode=3D1.25 Cgdmax=3D80p Cgdmin=3D12p Cgs=3D50p Cjo=3D= 50p Is=3D. 04p mfg=3DFairchild Vds=3D60 Ron=3D2 Qg=3D1.5n)

The Q of the tank makes it start slow. The symmetry is bad, too.

I intend to produce these, optimistically a lot of them. All sorts of fet thresholds will happen. I can't afford for some percentage of them to blow fuses or hang my startup or whatever.

Spice can be dangerous. It doesn't prove that a circuit is safe.

If my 12 volt supply current-limits and the Baxandall doesn't start, on even 1% of the units, it will be big touuble.

I'll probably go with the FPGA-driven flyback.

The Baxandall diversion was interesting, so thanks for bringing it up. Knowing things like this often turns out to be useful later on.

It's still an interesting problem, to design a mosfet Baxandall that starts up nicely. The bipolar version is nicer in that respect. Baxandall even did the trickle-current plus diode startup trick, something I invented independently for motorcycle CD ignition inverters.

John

Looks like this topic has been beaten to death by now, lots of solutions. But I see they are all open loop.

If you are running close to abs max with bias I'd at least add some sort of angst limiter. If would be sad if some other regulator has a bad day, rears up and then some four-digit Dollar amount burns up in the photodiode without even letting off a bang.

A cap multiplier probably can't hurt either, to muffle the ripple.

--
Regards, Joerg

http://www.analogconsultants.com/

seen this?

-Lasse

Nah, whatever works.

Being a one-man band at present, I like things that can be tested readily in sections. Having to get the whole back end working in order to test the front end wouldn't be my first choice. You folks are doing mainly digital stuff, with the analogue as an appendage, so I imagine that isn't a worry in your situation.

Any other analogue stuff hanging on there would certainly thank you.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510
845-480-2058

hobbs at electrooptical dot net
http://electrooptical.net

I'm certainly going to breadboard it, partly because I enjoy breadboarding things. I can drive the fet from a pulse generator and determine what works at various frequency and duty cycles, and then tell the FPGA lackey what to do.

But we do analog stuff, and the digital is the appendage. Anybody can do digital... you just have to be able to count to 1.

The box with the HV supply in it works with mostly high-level signals, from a separate preamp box, and has nothing more radical inside than a

200 MHz, 12 bit ADC. Hah, no big deal.

The HV goes out over a cable to the preamp box. It hangs on a vacuum flange, cantelevered on some hermetic high vacuum BNC connectors. On the vacuum side of the flange is the photodiode itself, nicely shielded by about $10K of stainless steel piping.

The EUV flashes are pretty ratty, so if I make them a little worse I'm unlikely to get caught.

John

Huh? Just because a Tesla coil isn't within that fifty-year window, doesn't mean it isn't prior art.