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VHDL if/when

I read in sci.electronics.design that Paul Burke wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

hazy

If you don't, one of them will get up and bite you. Eventually.

--
Regards, John Woodgate, OOO - Own Opinions Only.
If everything has been designed, a god designed evolution by natural
selection.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
Reply to
John Woodgate
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study it a

in

In normal use, 'when' generally implies that an event will happen, or has happened, at some time. Whereas 'if' covers things that may never be so. For example, I would say "when" not "if" I die.

But of course people don't strictly use them this way.

Programming languages seem to start off with Boolean branching:

if { boolean_condition } = { true } // usually implicit! then { action_when_true } else { action_when_false }

as the simplest conditional statement (only two possible outcomes of true and false), then make key words for branching more than two mutually exclusive ways.

if { an_integer } = { 1 } then { action_1 } = { 2 } then { action_2 } = { 3 } then { action_3 } else { action_default }

The choice of syntax is not so obvious. C uses

switch { an_integer } case 1: { action_1 } case 2: { action_2 } case 3: { action_3 } default { action_default }

VHDL uses

case { a_hex_digit } is when x'1' => { action_1 } when x'2' => { action_2 } when x'3' => { action_3 } when others => { action_default } end case;

I suppose the 'when' implies inevitability that one of the conditions must apply.

All human-invented languages, for humans or machines, seem to re-use words in multiple contexts...

Reply to
Kryten

"Paul Burke" a écrit dans le message de news: snipped-for-privacy@individual.net...

I'm not sure to understand. You speak of states. Is it for state machines or signal state in general?

The rule is that a signal that is not assigned a value holds its state. So it's easy to inadvertly synthesize latches for example.

sig1

Reply to
Fred Bartoli

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