VHDL if/when

I read in sci.electronics.design that Paul Burke wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

Try alt.philosophy 101?

'If' and 'when' are used as keywords in several very different constructs, so I'm going to assume that you mean these 2 common constructs:

if BOOLEAN_EXPRESSION_TRUE then SOME_SIGNAL

"Paul Burke" a écrit dans le message de news: snipped-for-privacy@individual.net...

WHEN is a concurrent(parallel) statement.

IF is a sequencial statement and has to be used within a process. Be careful with the implications.

Of uncomplete IF or WHEN assigments (unintended latches...).

I don't know why they choosed different names. Probably to emphasize the difference between // en sequencial assigments... maybe.

I read in sci.electronics.design that Fred Bartoli wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

That's the dull answer. (;-) Mine is that if it refers to something good happening , then 'if' is correct. If it refers to something bad happening, then 'when' is correct.

I read in sci.electronics.design that Fred Bartoli wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

Of course. But OT philosophy is even more fun.

If I knew then what I know now... When the roll is called up yonder...

If your breasts are too big You will fall over, Unless you wear a rucksack. (Ivor Cutler)

But that doesn't get the baby washed. What i'm trying to work out is exactly what it means in terms of the logic that gets synthesised. I suppose what I'm saying is that I'm hazy about what happens in states I don't define: is it best practice to define all possible states?

Paul Burke

In normal use, 'when' generally implies that an event will happen, or has happened, at some time. Whereas 'if' covers things that may never be so. For example, I would say "when" not "if" I die.

But of course people don't strictly use them this way.

Programming languages seem to start off with Boolean branching:

if { boolean_condition } = { true } // usually implicit! then { action_when_true } else { action_when_false }

as the simplest conditional statement (only two possible outcomes of true and false), then make key words for branching more than two mutually exclusive ways.

if { an_integer } = { 1 } then { action_1 } = { 2 } then { action_2 } = { 3 } then { action_3 } else { action_default }

The choice of syntax is not so obvious. C uses

switch { an_integer } case 1: { action_1 } case 2: { action_2 } case 3: { action_3 } default { action_default }

VHDL uses

case { a_hex_digit } is when x'1' => { action_1 } when x'2' => { action_2 } when x'3' => { action_3 } when others => { action_default } end case;

I suppose the 'when' implies inevitability that one of the conditions must apply.

All human-invented languages, for humans or machines, seem to re-use words in multiple contexts...

"John Woodgate" a écrit dans le message de news:prMgdJS$ snipped-for-privacy@jmwa.demon.co.uk...

it

I can see you're more inclined to the fun of analog design than to the boredom of digital piling.

I read in sci.electronics.design that Paul Burke wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

If you don't, one of them will get up and bite you. Eventually.

According to

'When' is a lot more like a conditional assignment - almost like a 'case' statement,

The 'if' branches (or not) - the 'when' always executes straight through, with the output specified by what the conditions were when it executed.

Hope This Helps! Rich

"The signal assignment can be extended by the specification of conditions. The condition is appended after the new value and is introduced by the keyword ' when '. The keyword ' else ' is also strictly necessary after each condition as an unconditional signal assigment has to be present. Consequently, it is not possible to generate storage elements with an conditional signal assignment. Otherwise the behaviour is equivalent to the if ..., elsif ..., else ... construct that is used within processes."

A when is an assignment statement - in my head, it's resolving into a data selector, albeit I have no idea what's actually happening, while an if is more like a branch in the execution path. Maybe the if does something sequential.

Why not write some and see what it compiles to? :-) I'm tempted to do it myself, except I'm on Linux and the Xilinx ISE I downloaded is on the Windows side. )-:

Cheers! Rich

"Paul Burke" a écrit dans le message de news: snipped-for-privacy@individual.net...

states I

I'm not sure to understand. You speak of states. Is it for state machines or signal state in general?

The rule is that a signal that is not assigned a value holds its state. So it's easy to inadvertly synthesize latches for example.

sig1

study it

in

According to

'When' is a lot more like a conditional assignment - almost like a 'case' statement,

The 'if' branches (or not) - the 'when' always executes straight through, with the output specified by what the conditions were when it executed.

Hope This Helps! Rich

No, as others have said, WHEN/ELSE is a concurrent construct and IF/THEN/ELSIF/ELSE is a sequential statement. They're used in different places (IF must be in a Process and WHEN can't be in a process). They're quite similar, otherwise. Both can produce similar logic.

Yes,! That's really the difference.

They can be used to infer *intended* latches too. For instance (doing this in Synplify and the Xilinx libraries):

Data_out

"John Woodgate" a écrit dans le message de news:prMgdJS$ snipped-for-privacy@jmwa.demon.co.uk...

wrote

if/when', on

study

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good

I can see you're more inclined to the fun of analog design than to the boredom of digital piling.

I read in sci.electronics.design that Fred Bartoli

wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

study it

in

That's the dull answer. (;-) Mine is that if it refers to something good happening , then 'if' is correct. If it refers to something bad happening, then 'when' is correct.

I read in sci.electronics.design that Fred Bartoli

wrote (in ) about 'VHDL if/when', on Tue, 20 Sep 2005:

the

Of course. But OT philosophy is even more fun.

good

If I knew then what I know now... When the roll is called up yonder...

If your breasts are too big You will fall over, Unless you wear a rucksack. (Ivor Cutler)

But that doesn't get the baby washed. What i'm trying to work out is exactly what it means in terms of the logic that gets synthesised. I suppose what I'm saying is that I'm hazy about what happens in states I don't define: is it best practice to define all possible states?

Paul Burke