two CPLD's on the same board??

The main thing to remember is that the speed beetween the two devices will be much slower than the internal speed of the PLDs. But this won't be too much of a problem if you partition the logic sensibly, and take care when routing between the devices.

"Toma" schreef in bericht news: snipped-for-privacy@75g2000cwc.googlegroups.com...

Difficult to say without knowing the design. I've ever done so with a small design in which speed was not an issue. Of course you'll have to split up the design and define the way the two parts communicate which each other. But the first thing I'd do is contact Altera for support. They may have advised in similar problems before. Maybe a more skilled designer can even reduce the required sources to make the design fit in one component. Ever got such a solution with a SPARTAN device. (Don't know your skills of course.)

petrus bitbyter

You'll need to split your design at a point where you'll need least signals to go to the other fpga.

I did something similar on a design I'm working on. Because I needed a lot of pins but didn't want to use the BGA package, I choose to spread the design over 2 fpgas. In my case it is easy because both fpgas do almost the same so most logic is duplicated. All I need are 3 synchronisation signals between the fpgas. The downside is that the uC on the board needs to configure 2 fpgas which takes a little bit more time.

The old Max Plus used to be able to split designs across devices. The Lastest Quartus To my knowledge does not.

Cheers