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Transfer function of DDS

Hi all,

I wonder if anyone has figured out the transfer function of a direct digital synthesizer, from reference clock input to DAC output? Actually I only need to know whether it has an 1/z behaviour (integrator type) or linear. I use a DDS within a PLL loop as frequency divider and have serious stability problems.

For those who are interested: An ADF4002 PLL is fed with a 3Vss rectangular reference signal in the

10k-100MHz range. The other (RF) input is tied to one DDS output of a 4 channel synthesizer (AD9959) via a 180MHz 7th order Bessel low pass filter and a comparator which ensures sufficiently low rise time at low frequencies. The input level here is 550mVpp. The PFD output is routed via the loop filter (lead-lag type at 400Hz at the moment) to a MAX2608 VCO running at 400MHz (370-430 over the full tuning range).

By now, the PLL locks almost when run at a reference of 1.84MHz, the DDS also set to 1.84MHz and the ADF4002s internal dividers set to 1. It locks perfectly when the DDS ist set to 3.68MHz and the RF divider is set to 2. It will never lock at the design target frequency of 10kHz at the PFD, realized by divider ratios of 184.

Reply to
Stefan Huebner
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So you're driving the DDS from the VCO? I'd model the VCO as something that takes voltage and integrates it to phase, I'd model the DDS as a gain stage (with gain

Reply to
Tim Wescott

DDS transfer function from the clock to the output is no different from that of the frequency divider. It has a comb FIR action (z[-1]).

A silly question: You are operating PLL at the very different parameters of the loop. Are you adjusting the loop gain and the loop filter accordingly?

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

Hi Stefan,

I noticed your question in d.s.e. before.

Look @ your control voltage, when the divider ratio is very big. you will never get a really stable voltage, even with a filter of very high order. May be it works better, if you feed your control signal into a sample & hold and hold this value through the time until the next phase arrives.

PLL in such a big frequency range (10 kHz up to 100 MHz???) is a very strange topic.

Marte

Reply to
Marte Schwarz

Good to know, I got that point this afternoon and brought it into my thread on de.sci.electronics already.

At the moment I was hoping I could eliminate all the trouble by making it slow enough for all frequencies in question.

What, in your opinion, would be a manageable frequency range or ratio for a PLL using a DDS as divider?

Reply to
Stefan Huebner

At the moment, I get no control voltage (or almost no) when using a high prescaler. The PFD output is stuck at the lower end, generating stochastic output or a sawtooth signal, all of them with an average voltage far below the VCO tuning voltage for mid frequency.

I know. And I think I'll have to split this range, probably by switchable loop filters.

As written in dse, I'll draw some diagrams this evening and put them on a web site.

Thanks so far :)

Reply to
Stefan Huebner

It depends on the performance required. The performance degrades proportionally to the high/low frq. ratio. Taking the reasonable assumptions, I would not advise covering the range higher then 100 times without adjusting the loop parameters. So the 10kHz...100Mhz band should be split into two subbands at the very least.

Vladimir Vassilevsky

DSP and Mixed Signal Design Consultant

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Reply to
Vladimir Vassilevsky

For those who already participated and those who will hopefully join in, I've uploaded the first schematics to:

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The loop filter is now based upon trial and error, in the mean time I tried component values based on ADISIM PLL calculations with a lead and lag filter plus two additional low pass filters.

Being calculated for a PFD clock of 10kHz, it only works stable with the ADF4002 set to R=1 and N=2 (maybe also for higher N's, but definitely not for R=N=184 and 1.8MHz external reference clock).

The reference is a 1.8432 MHz XTAL oscillator connected to the SMA plug on page 2 via a 470R resistor.

Reply to
Stefan Huebner

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