I wonder if anyone has figured out the transfer function of a direct digital synthesizer, from reference clock input to DAC output? Actually I only need to know whether it has an 1/z behaviour (integrator type) or linear. I use a DDS within a PLL loop as frequency divider and have serious stability problems.
For those who are interested: An ADF4002 PLL is fed with a 3Vss rectangular reference signal in the10k-100MHz range. The other (RF) input is tied to one DDS output of a 4 channel synthesizer (AD9959) via a 180MHz 7th order Bessel low pass filter and a comparator which ensures sufficiently low rise time at low frequencies. The input level here is 550mVpp. The PFD output is routed via the loop filter (lead-lag type at 400Hz at the moment) to a MAX2608 VCO running at 400MHz (370-430 over the full tuning range).
By now, the PLL locks almost when run at a reference of 1.84MHz, the DDS also set to 1.84MHz and the ADF4002s internal dividers set to 1. It locks perfectly when the DDS ist set to 3.68MHz and the RF divider is set to 2. It will never lock at the design target frequency of 10kHz at the PFD, realized by divider ratios of 184.