faster DDS clock

The usual trouble is that you have to get the other edge from somewhere. An xor gate and an RC is typical.

Any asymmetry in the square wave turns into subharmonic jitter.

A 2:1 PLL would probably get my vote.

Cheers

Phil Hobbs

How important is it that the duty cycle is 50%?

I'm trying to make things cheaper and simpler. I need a clock that's programmable up to maybe 20 or 25 MHz, and it would be nice to use some relatively cheap dual DACs.

Not super critical. The product is an arbitrary waveform generator and a small wobble in the output sample timing won't be noticed.

I'm thinking I can keep the duty cycle close to 50%.

The falling-edge jitter should be about the same as the rising edge jitter.

A dual DAC would save me a lot of data lines, so maybe I can go from single-8 to a dual-10 DAC or something.

Understood. A Joergesque solution would be to use a discrete FET as part of the RC + XOR, and dork the ON resistance to square up the duty cycle. (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe it’s possible to use a TinyLogic inverter with VDD open.)

Cheers

Phil Hobbs

An LVDS line receiver would make a pretty good comparator, after the filter.

If I have enough balls (no pun intended) I can use an LVDS input of my FPGA. One could even servo that to exactly 50%.

I don't know if this FPGA could internally clock on both edges.

But I can get a TI DAC908 for under $5, so may just clock that fast, brute force at 100 MHz or so. That would make 20 MHz with a dinky filter.

Doing that doubling trick when you take a sine wave oscillator and feed it via a comparator to the reference input of a PLL has a subtle advantage: Any additive 1/f voltage noise affecting the input stage of the comparator, or from any buffering stages for the sine wave before it gets to the comparator, will move the rising and falling edges of the comparator in opposite directions, and if both the rising and falling edges are clocking the phase detector of the PLL then the 1/f noise will cancel out at low frequencies and not make it through the loop filter, and not cause phase modulation of the RF output from the PLL. It's really a nice bonus. I guess it wouldn't work so well if the incoming waveform had asymmetric slew rates.

I can't feed my DDS into a PLL; frequency change has to be instantaneous, and cover a huge frequency range.

I'm generating waveforms that simulate a geared jet engine, which is a noisy shakey vibrating thing, so nanoseconds of jitter/phase noise doesn't matter much.

Using a synthesizer would be great, like an LMX2571... no filters or comparators needed. $7 and we'd be all done. But it takes way too much math to program.

this will give you 3x10bit@140MHZ DACs for about the same price

That's cool. I need 4 DDSs so I'd use two of them, but it is still appealing. It looks like I'll have to use an Efinix T130 FPGA to get the RAM I need for waveform storage, so I'll have tons of logic and i/o's to go hard parallel to the DACs.

I could use 10 or 9 or 8 bits if that is easier to route, and the current outputs dump right into the right kind of filter.

I have a Spice model of a DDS clock generator. I wonder how awful a lowpass filter I can get away with. CLC? Or even RC?

Active RC filters are a lot easier to design than anything involving an inductor. Close tolerance inductors are rare and expensive when they are available. 25 MHz calls for fast op amps, but you can find them.

Williams and Taylor is a useful reference - not as user-friendly as Don Lancaster, but a whole lot more comprehensive. And they do cover finite impulse response filters.

It occurrs to me that the use for a 3-channel fast 10-bit DAC is to drive a color CRT monitor, which I expect nobody makes any more.

you can probably get away with wiring the DAC datalines in parallel and use separate clock for each DAC, sorta like DDR

use DDR output with the data for each DAC, make the clock for each DAC use the other DDR outputs, one with 0,1 data the other with 1,0 data

It's for VGA (that's why it has sync and blank input) While VGA is old I doubt it is going anywhere soon, it still widely used, go buy a server and it has VGA

Seems silly to take digital data, convert it to analog, ship it six feet, and convert it back to digital.

And why do we have those firehoses of HDMI connectors and cables? Why not use Ethernet or USB out to a monitor?

HDMI is ~10-20 times the bandwidth of regular ethernet

there are plenty of monitors that can use USB-C

Maybe some gamers need multi-gigabit bandwidth.

I can watch a movie that arrives at my house over a cable modem and CAT5 or WiFi to my computers. So a CAT5 from the computer to a monitor should be OK.

That's sensible. The HDMI connectors and cables are klunky.

We really only need ethernet, USB-c, and one unified wireless/wifi network.

anyone that wants sensible refresh rates and better resolutions than was the norm 20 years ago do too

that's lossy compressed to the extreme and adds lots of latency which for a movie doesn't matter, but for a desktop display it would unbearable