Back in mid 2009, I was researching how to get rid of the DDS spurs and phase bumps discussed in the recent "DDS Wisdom" thread. I found many approaches, mostly applicable or implementable only by the chip manufacturer, but I did find one approach that can be implemented using commodity DDS chips covered by a now-expired US patent, 5,598,440 to Domagala, titled "DDS driven DDS synthesizer for generating sinewave waveforms with reduced spurious signal levels".
This patent also has a nice description of the causes of spurs.
Also be sure to look at the patents that reference this patent. These patents will point out the problems with the present patent, and propose solutions. All in all, a good source of ideas.
Be aware that this dual-DDS approach will not solve spurs due to truncation in the lookup tables. However, these kinds of spurs tend to be harmonic, so there can be a large reduction in close-in spurs.
I'm not clear on how the phase truncation spurs are minimized in this patent. They use two DDS, the first one (with phase truncation) to generate the clock rate for the second one which does not have phase truncation working with simple integer ratios. But that alone won't get rid of the phase truncation spurs of the first DDS.
They seem to be saying the filter and bandwidth magnifier somehow reduce these spurs, but I'm not at all clear on that. Filtering is always an option, but the issue is filtering is of limited utility for close in spurs. The bandwidth magnifier would appear to be an up converter. I don't see how this impacts the spurs. That seems to be more about getting the right clock rate to drive the second DDS.
I think this patent is about reducing the phase related (close in) spurs by a relatively modest amount by tweaking the filters between the first and second DDS along with the reduction in spurs that comes from the division by the second DDS which is boosted by the up conversion in the mixer(s). This imposes phase noise limitations on the LO, but since it is a fixed frequency this is not too bad. So they are leveraging the tunability of the first DDS while mitigating the spurs by up converting the frequency then reducing the spurs by the division by the second DDS.
When you talk about "truncation in the lookup tables", I believe you are talking about amplitude truncation due to the finite word width. These spurs can be controlled by making the word width as wide as needed with the ultimate limitation in the DAC really.
Phase truncation can be mitigated two ways. One is to use ratios of input clock to output clock that don't require long phase step words. That is what this patent does in the second DDS. The other is to use something other than a simple lookup table to generate the sine. A LUT can be used along with a linear interpolation to minimize the error due to the phase word. This can be *very* effective but quality varies with the phase angle, better near zero crossing and worst near the max and min values of sine. If the computing resources are available a second order term can be used which produces a much better result over the entire sine function. I have produced a linear interpolation which as I recall was good to 16 bits of output. And this was in a small FPGA with no hardware multipliers (step and add algorithm). I was using a 24 bit audio CODEC which produced a very clean signal. I was not able to measure the spurs since I don't have the equipment. But I might be able to collect samples after looping it back through the CODEC. It would be interesting to see what the system distortion is like. I'd have to set up my test fixture and see if I can catch samples. There's not much memory left on the FPGA.
I did the calculations for even better results. A 256 entry LUT with linear interpolation can yield accuracy to 5 ppm (~18 bits) and a 1024 entry LUT with linear interpolation can reach 0.3 ppm accuracy (~22 bits). I don't recall if I used a method of maximizing the end points to center the approximation line on the curve to split the error. This has the potential of cutting the error in half.
For high frequency signals 22 bits is not realizable in the DAC. But once you have a sine value that is this close to the "correct" value the phase error is essentially gone. Truncation (or rounding) of the amplitude produces random spurs related more to the incoming clock and harmonics of the output frequency and are not concentrated close to the carrier so they can be filtered.
I have not yet re-read the patent, But I think I recall that this was explained.
The second DDS is used as a frequency divider, so the spurs are likely reduced by the square of the division ratio, if it follows the phase-noise rule.
Yes, the object is to reduce close-in spurs. But I doubt that they would have bothered with the complication if the reduction wasn't significant.
Actually, both phase and amplitude. Typical DDS chip has a 48-bit phase accumulator, but uses the upper 12 to 16 bits (of phase) to drive the lookup table, and this table contains 10-14 bit amplitude values, so we have double quantization.
You can do pretty well by using a cable delay and a mixer in quadrature to cancel the carrier. What's left is all close in spurs and phase noise.
You are inventing a parallel to Solbrig's approach, which allows all quantization errors to be made insignificant if all digital (no DAC).
The SRS CG635 clock generator goes to 2 GHz with 1 uHz resolution and very low phase noise. The architecture is (as I recall) a DDS that covers a small range, feeding a narrowband bandpass filter, a crystal filter maybe. The output of that drives an N/M synthesizer with low phase noise. The DDS provides the resolution that the output synth can't.
Nice box, with the usual SRS quirks.
--
John Larkin Highland Technology, Inc
picosecond timing laser drivers and controllers
jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com
It is best to discuss the different sources of spurs separately since they are separate causes and separate effects. Also, when you mean DDS chip, you should say DDS chip and not DDS. There are many, many DDS designs that aren't sold on a chip. Also, it is not a good idea to describe specific bit sizes unless you mean a specific chip as these numbers can always vary.
This is nothing like Solbrig's approach that I can see. Do you mean the patent we have been discussing or some other approach?
Ok, so was there anything specific you *are* saying? I don't know what you mean by parallel. It sounds like you mean "something different". Yes, generating the sine values with more precision is *different* from Solbrig's approach.
I don't have the energy to walk you through each and every detail. You have both patents. Compare them.
Another approach is to build or simulate the two models. Actually building and testing will clear up all manner of issues.
Both kinds of DDS are very simple to code in C or MatLab (or assembly code, for best performance), to quickly generate yards of simulated sampled output that can then be analyzed for spurs et al. No messy soldering required.
I really can't follow you sometimes. You commented that my personal approach to DDS design was "parallel" to Solbrig's approach. "You are inventing a parallel to Solbrig's approach, which allows all quantization errors to be made insignificant if all digital (no DAC)."
Now you are talking about two patents. What is the other one and compare them to what - each other or to my approach?
I told you what I found. The design is built. I don't have equipment to measure the spurs, but they will be mostly due to the DAC rather than the DDS because of the low error values. I can share the spread sheet with you if you wish. It contains the calculations for the values of the errors over a range of values.
This isn't rocket science. 15+ years ago the computation capability in many devices was more limited than what we can do today. A DDS calculates the values of the sine function to drive a DAC. Errors in the calculations generate spurs in the output. The problematic spurs are the ones close to the signal of interest since they are hard to filter out. These close in spurs are mostly generated by the phase truncation errors. By minimizing phase truncation errors the close in spurs are minimized. In the patent I read (it was actually Domagala
5,598,440) they use a combination of of clocking, filtering and frequency up conversion to minimize those spurs. This level of complexity is not needed if the calculations are done with minimal phase truncation. That is what I have done by using linear interpolation. I don't think linear interpolation is a new technique in any way. I would expect this to have been applied to DDS design previously.
One other thing that can be applied to the DDS approach is dithering of the rounding errors on the amplitude values fed to the DAC. When you have close in spurs they can be spread by the use of dithering. This raises the overall noise floor while lowering the spur.
You can learn about technology from older patents. But technology often advances so as to make patents obsolete before they expire. I think that may be what has happened in this case.
If you simulate your design in software, you will be able to estimate the spurs due to truncation pretty accurately. What you cannot estimate so well using a simple simulation is the effect of various hardware imperfections and tradeoffs.
Rather than just a spreadsheet, a design and principles of operation paper would be interesting.
Some chips interpolate. It's a big tradeoff exercise in chip real estate - which is better, a big LUT and no interpolation, a smaller table and an interpolator, a CORDIC algorithm, or something else, given a specified level of performance.
Sobrig went all the way on big lookup tables, no doubt implemented in a FPGA. My guess is that the software in the control computer figures out the one lookup table needed for the commanded frequency, loads the new table into the FPGA (or an attached DRAM), and commands the FPGA to start singing this new tone.
Circling back to the original question, Phil Hobbs is not looking to develop his own DDS chips. He is looking for a way to solve his larger design problem using commodity DDS chips.
Some chips do this.
Obsolete is a bit strong. What happens as the semiconductor performance increases by Moore's Law is that what had been the cutting edge becomes a commodity jellybean part, and its market penetration expands exponentially. There are two bounding paths: First, the latest best technology is implemented for people who value performance over price. Second, the older former best is implemented to a specified cost, for those people who value cost over all else.
Not sure I understand what you mean. What hardware "imperfections" are there? That's one of the huge advantage of digital hardware. It doesn't depend on the "quality" of implementation. Either it works or it doesn't. Simulation is perfect for analyzing tradeoffs. That's one of the main reasons for using simulation.
As to analyzing my design, that is not required for me. I can easily see this implementation surpasses any requirements I have. The spurs from the calculation of the sine values are on the order of -200 dBc. The DAC is only good to the 100 dB range for SNR, dynamic range and SINAD. Heck, the crystal clock itself is likely not as good as the sine calculations.
I'm not sure what you want. It is the same as what you have seen many times with the addition of a multiplier applied to the lower phase bits. This value is added to the output of the LUT to produce a more accurate sine value. The "principles of operation" have been described here. Do you have any specific questions? If you are asking me to post my VHDL code, I'm not able to do that at this time. This was a commercial application and i can't post the code.
LUTs are exponential in size requiring O(2^n) space in a device. So that clearly has limitations which is why the linear interpolation is useful. I found that even with a 256 item LUT the linear interpolation produces is a huge improvement as you can see from the results I've indicated.
If that problem is the close in spur problem then he is stuck. He can either limit the frequency ratios to those which do not produce phase truncation or use a chip that doesn't have the "DDS" label on it like an FPGA.
Everything in engineering is tradeoff. Often that tradeoff is between function and cost. No one puts cost ahead of all functionality. That would result in a design with nothing in it at all. The issue is how much you have to spend to achieve the required performance.
Digital hardware is implemented with analog components. For any single inpu t, a logic gate is just an analog amplifier (usually with a gain of about t en) which is nornally driven to one rail or the other.
Digital hardware has propagation delays (which can depend on the supply vol tage - and with TTL the rails tend to be "grassy" as individual gates pull it down while they are moving form one logic state to the other) - as well as set-up times and hold times (which also depend on the exact rail voltage ).
Sure, but there' stuff that simulation doesn't tell you about. I had to fix a TTL fast pulse generator because the output showed pattern-dependent mov ement in the position of the pulse edges - which I did by putting in a PECL stage, with an ECL-to-TTL converter to get the final output back to TTL le vels.
This was all about the sensitivity of the TTL propagation delays to the exa ct supply voltage on the silicon at the gate. Because ECL is current steeri ng logic, the current drawn by the device is pretty much constant, so the s upply voltage on the chip can be stable, and I made sure that the noise on the TTL +5V rail didn't get into the PECL +5V rail.
put, a logic gate is just an analog amplifier (usually with a gain of about ten) which is nornally driven to one rail or the other.
oltage - and with TTL the rails tend to be "grassy" as individual gates pul l it down while they are moving form one logic state to the other) - as wel l as set-up times and hold times (which also depend on the exact rail volta ge).
ix a TTL fast pulse generator because the output showed pattern-dependent m ovement in the position of the pulse edges - which I did by putting in a PE CL stage, with an ECL-to-TTL converter to get the final output back to TTL levels.
xact supply voltage on the silicon at the gate. Because ECL is current stee ring logic, the current drawn by the device is pretty much constant, so the supply voltage on the chip can be stable, and I made sure that the noise o n the TTL +5V rail didn't get into the PECL +5V rail.
That is all analog problems and have absolutely nothing to do with the impl ementation/simulation of the digital parts of a DDS
there is no imperfections, it is all math. if the implementation doesn't produce the exact same bit pattern as the simulation it is broken
You can bet that most DDS chips use some kind of Sunderland compression. It can gain a factor of 12 to 50 times in storage bits. Costs maybe one more pipeline stage ( i.e. 1 adder) and divides the ROM into 2 much smaller ones.
<
formatting link
>
I hope that this monster url works :-) Crawford mentioned this in his frequency synthesizer book.
On Friday, 19 December 2014 09:18:36 UTC+11, Lasse Langwadt Christensen wr ote:
]]
re
input, a logic gate is just an analog amplifier (usually with a gain of abo ut ten) which is nornally driven to one rail or the other.
r
voltage - and with TTL the rails tend to be "grassy" as individual gates p ull it down while they are moving form one logic state to the other) - as w ell as set-up times and hold times (which also depend on the exact rail vol tage).
fix a TTL fast pulse generator because the output showed pattern-dependent movement in the position of the pulse edges - which I did by putting in a PECL stage, with an ECL-to-TTL converter to get the final output back to TT L levels.
exact supply voltage on the silicon at the gate. Because ECL is current st eering logic, the current drawn by the device is pretty much constant, so t he supply voltage on the chip can be stable, and I made sure that the noise on the TTL +5V rail didn't get into the PECL +5V rail.
plementation/simulation of the digital parts of a DDS
Wrong. If the clock edges move because of pattern dependent changes in curr ent draw and thus rail voltage, within the chip, this will show up as spurs on the real frequency output, and it's unlikely to show up on the simulate d output.
Den fredag den 19. december 2014 01.00.53 UTC+1 skrev Bill Sloman:
. ]]
are
e input, a logic gate is just an analog amplifier (usually with a gain of a bout ten) which is nornally driven to one rail or the other.
or
ly voltage - and with TTL the rails tend to be "grassy" as individual gates pull it down while they are moving form one logic state to the other) - as well as set-up times and hold times (which also depend on the exact rail v oltage).
to fix a TTL fast pulse generator because the output showed pattern-depende nt movement in the position of the pulse edges - which I did by putting in a PECL stage, with an ECL-to-TTL converter to get the final output back to TTL levels.
he exact supply voltage on the silicon at the gate. Because ECL is current steering logic, the current drawn by the device is pretty much constant, so the supply voltage on the chip can be stable, and I made sure that the noi se on the TTL +5V rail didn't get into the PECL +5V rail.
implementation/simulation of the digital parts of a DDS
t
rrent draw and thus rail voltage, within the chip, this will show up as spu rs on the real frequency output, and it's unlikely to show up on the simula ted output.
what? it is synchronous logic, the edges can move around as they like as lo ng setup and hold it satisfied. Your computer produces different results ba sed on voltages and propagation delays?
It got there, but had a complaint in German that I think meant that this page was not available. What page was it? Amazon and Google often differ in that is presented. I did fins a chapter on compression starting on page 49.
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here.
All logos and trade names are the property of their respective owners.