Special AND-gate

I'm not quite certain that randomness gates qualify as standard parts.

Absent any other constraints, just alternate between presenting a and !a at the output, since !(a && b) is equivalent to (!a || !b) and that's satisfied by !a.

FPGA PIC AVR PLC PGA Did I miss something?

In what way is the output dependent upon the inputs if the output has a 50/50 chance of being either 0 or 1? Maybe you should call it a "WHATEVER" gate, rather than an AND gate.

The "maybe gate", the digital kin of the "inoperational amplifier".

Easy,

if (A && B) generate a random 1 or 0 on the output;

Repeat forever;

Something must be getting lost in the translation because there is nothing you can do about the input combination occurring 1/4 of the time.

You can't do that for a strictly combinatorial circuit, it will have to be made sequential. The only combinatorial function that will produce 1 or 0 with equal probability is the parity function.

He can economize even more than that, just say it's 0 all the time, then he can only be wrong 25% of the time...

"Bernd Schneider" schreef in bericht news:Xns9A789C09B8ABberndschneider90yaho@194.177.96.78...

The function of an AND-gate is fully specified. Its output depends only on the inputs. So the probability of its output depends on the probability of its inputs. In other words, you do not want an AND-gate but something else. As you reasoning is unclear to me, I can only guess you to want an XNOR-gate. Out of four possible input combinations it makes two times true and two times false. See truth table below.

a b aXNORb

This function is also determined. The probability of the output still depends on the inputs.

petrus bitbyter

That's a parity function...

Yep, MSP430 for example. Or if Bernd wants the leather-seat deluxe edition maybe an ARM core.

Are you sure this is what your homework assignment said? Maybe it said "same probability of 1's and 0's" in which case you can use multiple outputs for the encoding.

As for the big list, add CPLD :-)

Fred Bloggs wrote:

The George W. Bush flip-flop by Mark Zenier news:cloi2g$tv5$ snipped-for-privacy@eskinews.eskimo.com

I kept thinking *fuzzy logic*.

Perhaps trot the two inputs down a pair of shift registers and do majority logic? That should certainly give some "randomness".

...Jim Thompson

Fred Bloggs wrote in news: snipped-for-privacy@nospam.com:

What is a combinatorial circuit? And what is with the XOR function? for two random bit inputs it outputs 1 with probability 1/2

What I acutually try to achieve is an AND gate that flips its output with probability 1/2 for random input. So assume in the first clock cylce you input two random bits to the AND gate. The output will be 1 with probability 1/4 and 0 with probability 3/4. Now, for the next clock cycle, again for random input we have with probability 1/4 an output of 1 and with probability 3/4 an output of 0. The probability that at the output wire we have a flip is 6/16, but what I acutally want to achieve is that the output wire flips with probability 1/2. If I consider for instance an XOR gate than the probability that the output flips is always 1/2. Can I achieve the same probability also for an AND- gate without losing the functionality of the AND-gate?

Cheers, Bernd

DJ Delorie wrote in news: snipped-for-privacy@delorie.com:

Yes, multiple outputs are definitly allowed to solve this problem... but I am not so sure how it can help.

Probably the secification of my problem was not very well stated.

I hope my second post makes things a bit more clear, although I am still not sure if it is possible at all to achieve something as I mentioned in my post from below.

Cheers, Bernd

John Fields wrote in news: snipped-for-privacy@4ax.com:

So, there is no way of designing an AND gate such that the probability of a flip at the output is 1/2?

No, because then it wouldn't be an "AND" gate...

Drop the "AND" from your specification and tell us the truth table, or output as a probability FUNCTION OF THE INPUTS and maybe we can help you design this bernd-gate.