PWM frequency divider

Why? What do you want to do if the duty cycles go as, say, 10%, 20%,

One way: divide the leading edge (assumed to be evenly spaced, with the trailing modulated) by 4. Integrate the "on" time for 4 input cycles. "Deintegrate" that value during the next output cycle to determine the "on" time for that cycle. Have two integrators that swap back and forth between the two tasks of integrating and "deintegrating". Easy enough to do in a 6-pin microprocessor, if the instruction cycle time of the uP is short enough for your required resolution. But there's a 4/90 second delay with this scheme.

I've been thinking about something similar recently.

You need a 2x D-types for a divide by four, 2x counters, 2x R-S flipflops, some gating, and a clock (not less than 10Khz for about 1% resolution on the output 22.5KHz PWM).

__ __ __ __ _ 90Hz | | | | | | | | | _____|T1|_____|T2|_____|T3|_____|T4|_____| 90Hz ________ ________ | _ /2 | | | | | | _____| |________| |__|_____| /2 _________________ _ /4 | | | | ____/|\\ |___________|____/|\\ /4 Set Set __ __ __ __ | _ | | | | | | | _____|T1 T2 T3 T4|_________________|_____| 22.5Hz

|_____________________________| _ | | | _____| Counter1 gating signal |_____|

Gate Counter1 to accumulate 10KHz clock pulses for the period T1+T2+T3+T4. At the end of T4, transfer the total count to Counter2, and Zero it The end of T4 is signalled by the 90Hz, /2, and /4 waveforms all being down.

Use the Set output from /4 to set an R-S flipflop, whose output is the 22.5Hz.

Also use the R-S output to Start the countdown of Counter2, clocked by the 10KHz, (and to reStart the Counter1 T1+T2+T3+T4 accumulation).

When Counter2 reaches Zero, Reset the o/p R-S flipflop.

The output duty cycle is then (T1+T2+T3+T4)/4*T.

The sequence can either be done in hardware or a uP.