# 24Hz to 60Hz PLL?

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I need to make a PLL that slaves to a 24Hz square wave. The output of the loop would be a 60Hz square wave. Any CMOS level chips that would be good for this? I understand that I would need to divide by a decimal value of 2.5 for the loop.

Thanks, Chris Maness

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You could phase lock the 24Hz (movie frame rate?) to a 120Hz VCO divided by 5, and divide the 120Hz by 2 to get 60Hz.

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The lcm of 24 and 60 is 120. This suggests the best you'll get is 5/2 if looking for exactness. i.e., 5*24 = 120 = 2*60

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CD or HC 4046, with a slow loop. Divide 24 by 2 and divide 60 by five and lock at 12 Hz. There's some old IC (7490?) that will do both divides for you.

John

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That sounds better than trying to find a divide by 2.5. What chips would suggest to accomplish the divide by 5? Are there complete PLL chips that can be programed to divide by an odd number?

Yes, it is a 1 pulse/frame to pilot tone converter. Similar to:

However, this is not primarily intended to have a record level sine wave out like "The Film Group" unit. I need a full 12V swing as an input to a perforated tape deck for the sync motor in the unit. Ideally I could have a lower level output to a digital recorder. This could in turn be amplified upon playback and fed back to the perforated tape deck. This would "resolve" the speed variations from the camera. When the film is played back referenced to a crystal, it would be synced to the film once the film has been scanned in to a frame accurate telecine.

Thanks, Chris Maness

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Or divide the 24 Hz by 2 and lock a 60 Hz PLL to the 12 Hz by a divide by 5.

Same thing but your soln. has higher frequencies so smaller caps.

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Use a PIC.

Lock on 24 Hz by input capture, generate 60 Hz by output compare. Do all PLL logic in software. There will be a jitter of +/-1 timer clock, however this will be much better then suggested analog solutions.

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Low frequency PLL's often present competing needs for fast lock and low jitter. So I've always been fond of this approach which "jerk" locks an "oscillator" created with a shift-register and a stable clock (dating back to 1983, where I had to extract data from a floppy whose orientation and physical acceleration were PITA)....

...Jim Thompson

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| James E.Thompson, CTO                            |    mens     |
• posted

of

ld

Here is what I have so far:

Looking at the CD4046b data sheet, it looks like the most straight forward design would be a Camera --> NE555 (to lengthen the 5ms pulse from the camera to 21ms for real square wave. I am not sure if this would be needed by the comparator)--> CD4046 (With an Divide by N CD4059 dividing by 5)-->CD4060 ( Signal Out from Q2 would be divide by

2).

I already have a bunch of CD4060's from my last project. I also have some NE556's. Seems very easy.

Thanks, Chris Maness

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Chris a écrit :

PLLs a those low frequencies are real slow if you need some 'jitter free' output.

Square waves have only odd harmonics. You could square up your 24 Hz, apply it to a narrow 120Hz BPF, then divide by two.

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Thanks,
Fred.```
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Just another reason for doing it in the software. You can achieve an approximate lock just in one period and then fine tune it as accurate and low jittery as you need.

I have to synchronize different clocks to GPS 1Hz output to the accuracy of 1e-9 or so...

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

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Yup, except that you don't need the 555 if you're using a digital in -- for that you want to use the 3-state phase/frequency comparator in the

4046, which is edge sensitive anyway.
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Hi Vladimir, Is there good reading references for doing a software PLL anywhere. So far in my casual searches, I've found very little on a software implementation.

Cheers

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As JL suggested, the 74HC390 (modern dual version of the old 7490 with power pins in the normal positions) will give you both divide by 2 and

5, with half a chip left over.

Best regards, Spehro Pefhany

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"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com```
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No, but here you go. This will be a complete document, with introduction, discussion, analysis, and a conclusion:

Making digital PLLs in software is fun and easy (introduction).

They're just like hardware PLL's (discussion)

except where they're different (analysis).

But they're easy, if you think hard. So go do it! (conclusion).

Was that too terse?

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Sort of. Thanks

Cheers

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How accurate is the 24Hz? How good does the 60Hz need to be?

You can take a crystal and divide it down to make the 60Hz and then make the counters get reset at a 12Hz rate to force it to be in step.

An HC4046 will lock in just a couple of cycles if you use the edge operated phase comparator. You can multiply up to several hundred Hz to make the component values for the oscillator more reasonable.

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f
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1. >

In PLLs it is better to multiply up first then down.

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f
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No, the 8051 is the right processor for this.

[ducks]
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A simple and straightforward method:

for(i = 0; i < N; i++) if ((i + k) % M == 0) recompute k, toggle clock;

Choose N, k, M appropriately. The loop is synched to the first clock. This method only works when increasing the clock speed but has a similar method for the opposite case. If N can be appropriately chosen then k can be set to

0.

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