Power Planes and Bypass Capacitors

Jun 20, 2009 24 Replies

I am planning to have a five layer board with a standard thickness of



1/16". Three of the layers will be for power planes which will have +5V, gnd, and -5V. This will make the power planes a large capacitor throughout board. Would additional power bypass capacitors still be necessary for the op amps and the digital control part of the CMOS analog switches?
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Yes.

The capacitance of the board alone will be far too small.

Try this

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Dielectric constant of FR4 is around 4.2

PCB stack-ups have an even number of layers.

Why not 6? No one makes a "five" layer board, you'll have six whether or not you want them.

Large how? You've given us no sizes to work with.

Yes!

You could probably get away without it, but opamps especially may have some low-frequency power rail current surges, so some added capacitance is prudent. Scatter some, maybe, 0.33 uF ceramics around the board, a few from +5 to ground and a few -5 to ground. Location doesn't matter. An aluminum or two wouldn't hurt either. A lot depends on whatever voltage regulators are making the +-5... some are unstable with just ceramic loads.

The power-to-ground plane capacitances will be roughly 100 pf per square inch of board (depending on your stackup) and you can't get a better high-frequency bypass than the planes.

Five layers is kind of strange. You can probably get 6 for the same price. Or share the +-5 on one plane and go down to 4.

John

Yes, 4 layers make more sense. Most of the noises will be coming from the +5 digital supply. The -5 plane can share a small area of the power plane.

Speaking of layouts, I have some questions of my own.

I am trying to fit a 2.5GHz RF transceiver in a narrow strip. By altering component placements, how would it affect the RF property. In particular, is it possible to place chips inside a mirrored F antenna?

See:

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The power supply will be mounted on the board. It is an Acopian DS-15:

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I need only 5 layers. I have had 5 layer boards fabricated before. I did not ask for the details of how they did it. My assumption is it was four boards laminated together. Under this assumption three boards are one sided and one board is two sided.

The component surface layer and the layer just under it are for routing. The third layer down is the ground plane which acts as an electrostatic shield against any power supply ripple. The 4th layer is +5 and the bottom layer is -5.

The ground layer would also act as a magnetic shield at frequencies where skin effect is thinner than the copper.

The board dimensions are not known exactly right now but will be in the vicinity of 3" x 5".

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Looks expensive. And probably has 60 Hz magnetics, so leaks AC mag fields.

That's a bit unusual. A more common stack would have the signals on 1 and 5, where you can get at them if needed. Ground would be 2 or 3.

You're trading signal-signal crosstalk (your layers 1 and 2) against conjectured power-to-signal crosstalk, which I'd argue is easier to control.

Magnetic shield against what?

What's it do?

John

It would be better to start a separate thread for this question, but anyway...

Neither of your proposals will work. An antenna needs space around it in order to function and in the first option you are filling up that space with components. In particular, the space between the inverted- F and the ground plane edge is critical to its operation. The antenna will be so severely detuned that it will have a tiny fraction of its intended output or reception performance. In the second case, you are removing the ground plane edge which the antenna requires in order to remain tuned.

You would do far better to place a quarter-wave monopole at the end of the board. This is simply a strip of copper slightly less than 1/4 of a wavelength long at the operating frequency. The ground plane must be removed at the end of the board under the monopole antenna and there must be no other components or tracks beside it. You should also ensure that the rf transceiver is at the end of the board next to the antenna. The printed balun and series inductor for the harmonic filter may cause problems if the layout is altered.

A better and smaller solution might be to use a ceramic balun. However, while the data sheet gives the input impedance in receive mode it does not seem to give the transmit impedance. Perhaps there is an application note which would help in choosing such a component.

John

You will need bypasses You need to consider what frequencies are in the digital stuff, what frequencies the op-amps are supposed to amplify, how small of signal is in the op-amps and a bunch of stuff like that to know just how important the bypassing will be.

Unless your board is very tight, you can go down to a 4 layer board by sharing the +5 and the -5 layer. Alternatively, you can have two ground layers.

DS-15:

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No, you had a 6 layer stackup built and you only supplied 5 artwork layers. You assume wrongly. The cores have copper on both sides. You have an even number of layers to work with. Your assumption is making you needlessly stubborn.

"any"? You're dreaming.

If it was infinitely conductive and infinite in extent, sure.

You won't know until you build the board and have actual power supply leads in place. Generally, you need a few hundred uF, perhaps more if you have lots of circuitry. I've seen nasty problems on a digital board due to lack of bulk capacitance (we only had a couple hundred uF). A 1000 uF aluminum cap solved that problem. It's usually a good idea to have some 100 nF caps sprinkled around.

PCB houses usually do even number of layers. If you actually specified

5 layers, without a blanked layer, you got charged a premium.
Mark

Boards are made by sandwiching double-sided cores with uncured, uncoated layers, called pre-preg. The stack goes into a hot press, which causes the pre-preg to stick and then to cure. That's why there are always an even number of copper layers.

Cheers

Phil Hobbs

That's what I am afraid of. Any layout change would affect the rf property. I need to keep the width under 10mm. How about making the board with FPC and roll or fold it? I can accept some signal degradation, since operating range is around 20 feet only. Alternatively, I can use sma connector and external antenna, but it would be expensive.

Typically they are not (excepting perhaps some more complicated processes for blind and buried vias).

Usually the outer layers are pressed from pre-preg and copper foil. You need solid copper on the outside of a pressed assembly to allow electroplating of the through holes.

You could make a 5 layer board by only etching the inside of the bottom core and adding pre-preg and foil only to the top. It doesn't save any processing, hardly any material and the imbalance probably leaves the board prone to warping during manufacture and after.

You could plate part of the board edge and use that.

Best Regards: Baron.

The through-hole plating is electroless, is it not? They can plate holes with no pads when necessary.

Cheers

Phil Hobbs

Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net

The electroless step is really thin. It's just the primer for the serious copper electroplating. And that needs contact to all the holes.

John

If they do it is only enough to provide a conductive surface to electroplate. My local board house uses a process which coats the inside of holes with carbon to provide one.

They can etch away the copper leaving not much of a pad.

A process to make a double sided 1oz board is:-

Take an FR4 core with 1/2oz copper both sides.

Drill the holes.

Laminate uv sensitive resist film on both sides.

Expose and develop the resist leaving resist where you don't want copper.

Dunk it in various chemicals to leave some carbon inside the holes.

Electroplate 1/2oz of copper down the holes and where the resist isn't.

Electroplate a bit of tin on top to be etch resist.

Strip the photo resist.

Etch away the copper where the tin isn't.

Stick on the solder resist (if any).

Pass it through a tin dip and hot air knife leveler.

Not sure exactly how/where alternate surface finishes change the process.

The process is just the same for multilayer boards except you start with a pressed core which already has some copper layers in the middle and you have to be careful to align the drilling with those layers.

AFAIUI, they "activate" the holes by treating them with chemicals that provide a seed for very thin conductive elecroless plating of copper or carbon, and then serious thickness of copper is plated on top. I think electroless plating is essentially self-limiting in thickness, at least the stuff I've used has been.

It is a transimpedance amplifier board for two PIN photodiodes. The analog switches are for selecting a variety of TIA gains. The analog switches's digital controls are the only digital functions on the board. There is no clock.

The photodiodes will be reversed biased at 16V. I plan no voltage plane for the 16V.

The bandwidth of the TIAs are to be 1MHz. The A to D converters (which are off this board on a National Instruments PCI-6110) are 5 MS/s. There will be at least a four pole anti-alias filter at 2.5 MHz.

The lines to the PCI-6110 will be driven by the AD8042 line driver op amp:

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Because it can drive only 25pF at +/-5V power a stability network will be used to counter the 2nd pole in the feedback loop the op amp's output resistance makes with the capacitance of the driven line.

For this board there will be no need for magnetic shielding.

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