Power supply decoupling

Everything matters. The location of the capacitor, which way it faces, how far the vias are and the locations of the others. What you really hope is that there are no high Q tuned circuits formed by any of the capacitors and the inductances. Since the Xc of the bypass capacitor is near zero at high frequencies, you can be fairly sure that the Qs are low.

The layer to layer capacitance makes for a lot of low impedance bypassing at the GHz end of the spectrum. The Z0 of the transmission line formed by the two layers is really low. If you make sure that the layout guy doesn't put the capacitors in nice pretty rows, you will be ok with just many 0.01u, and a couple of bigger valued ones.

I would put the bigger capacitors so that one is near where the power comes onto the PCB and the other is as far from that as can be. Low ESR tant. would be what I would look at for them.

One thing to watch for is the planes getting "sawn in half" by all the via holes needed to do the routing. Remember that the current is drawn in little spikes of a billion amps. These currents have to flow through the plane from the bypass to the actual pad.

Why not just use 0306 caps that are meant to be used in low-ESL configurations? Every tried those?

What's wrong with rows? You see caps in rows around packages all over the place.

So why is the consultant pushing his octave-of-caps strategy? I'm not really asking you to read his mind, maybe just some insight as to why some people push that, while others push the "biggest cap value in a given package" principle?

Lower ESR is not automatically "better", esp if there's a LDO somewhere that needs a certain resistance to guarantee stability. See, it's this kind of stuff I want to avoid: unintended consequences.

Yes, I use unused-pad-removal. This lets me remove inner pads on vias so I can free up copper area. As long as the via has outer and inner pads, the plating action will occur.

Ludicrous. Have one ground plane and one plane for each major voltage. Keep the insulators between the planes thin, 5 mils or so, and put the ground plane between the two highest current power layers. Scatter

0.33 uF or so 0603 or 0402 caps around to bypass each plane. For something like an fpga whose power drain is fairly steady, I use maybe 4 caps per supply. If the CPU has big current steps (say, goes from sleep to multi amps instantly, or otherwise has low-frequency components to its supply current) you'll need enough bulk low-esr microfarads to handle that, too. The caps can be around the periphery of the chip, on top or bottom, but needn't be interior to the bga array unless it's convenient.

The multiple-value capacitor thing is idiotic voodoo bypassing.

John

How can people be so sure they know exactly what their hypothetical god wants?

Its the same mental process at work.

You need to replace this religious person with an artist.

I would suggest a physicist, but I doubt you have the budget to find the absolutely best solution.

There seems to be a new, growing profession: signal integrity witch doctor.

John

Shake that chicken bone and chant the magic mantra...

Using multiple values like he is suggesting has merit when there are specific known frequencies that you want to clean up off the power supply (like the various clocks, local oscillators, etc.). If you use caps such as Kemet, with good published frequency domain data, you can select a value whose impedance minimum occurs at one of the frequencies of interest. If you only have a few troublesome frequencies, then this can be effective (depending on the Z of the power distribution, the loads, etc). But for broadband noise suppression, its no more effective than the "big cap plus little cap" approach you usually see. Using the Q characteristic helps for specific frequencies, but it provides no additional help for broadband suppression. You still need low impedance across the entire band for that.

I've used this technique in RF designs to achieve high isolation among circuits on shared power. I don't think I've ever used more than 3 values in a design of this type, though. If there are too many values, it suggests to me that he is trying to solve too many individual (frequency) problems. It would be better to look for ways to subdivide the power distribution to localize individual problem frequencies. POL regulation is the way to achieve this.

Steve

Thanks, this is meaty stuff I can use. I'm up to my eyeballs in claims and counter-claims. I'm hitting the physics textbooks to read up on resonance. But again, it seems to me that the loop inducatnce of each cap is dependent on the layout, therefore reading off values from a datasheet is useless. Am I wrong?

The article "Using Decoupling Capacitors" debunks the theory of using multiple value decoupling capacitors. .

I never have. So far I've never seen a need to use a funny form factor capacitor. You can add normal shaped capacitors in parallel to get the low impedance.

Rows often mean that the routing of the capacitor connections is longer. It is best to sprinkle.

People often do things for what are really emotional reasons. They may have thought of the idea themselves or been told it by someone they respect. As a result they may be emotionally invested in the idea even though they can't justify it with logic.

I don't use the "biggest in that package". I usually use the one I can get from two suppliers. I generally make it a rule never to use a part I can't get from Digikey. I do this to protect myself against "Oh that will be 52 weeks".

Usually put very large highish ESR caps near the LDO when I use them.

Yes, this is a good thing to do. It avoids having to push the vias around to make paths for the pour.

That's right, but keep in mind that the whole plane-chip-capacitor structure is a pretty low-Q system. The idea of Spice simulating paralleled capacitor models is naiive.

I've never done a multilayer board that had high-frequency bypassing problems, and I keep reducing the bypass cap density. I know one guy who doesn't use bypass caps at all, and his stuff works too. We do sometimes have low frequency problems, like switcher ripple modulating cmos chip prop delay, or LDO instability.

Some day I may do a serious LDO rant.

John

This paper is reasonable for a board of logic. However, there is merit to using low self inductance cerramic caps in parallel with larger value oscons. That is, a 0.1uf in parallel with a 10uf doesn't seem useless to me. But putting a 22pf ceramic in paralle with a 100pf ceramic doesn't make much sense.

Not useless, there are geometric effects, but layout is important. Once you have a board available, measure the actual impedance with a network analyser (i.e. load the decoupling caps and butch a good RF connector into the area you are interested in).

Regards Ian

I don't think I've ever seen that done. One could plop a couple of SMA footprints on a pcb layout, power plane against ground, and do a VNA analysis to see what the resonances and impedances really are. I don't have a VNA, but I do this with a 20 GHz TDR, which is instructive.

That would cut through a lot of "theory."

John

guy.

Better yet, use 10uF or 22uF ceramics. They are smaller, cheaper, have lower ESR and ESL, and are more reliable than any aluminum foil capacitor.

John

John Larkin wrote: (snip)

I am looking forward to that.

The guys at Sun have a paper where they do that. As I recall, the main difficulty is that you're looking at impedances that are very, very low, so you're really stressing the dynamic range of a 50 ohm VNA.

Do you believe papers like this one? -->

(When I say "believe" I mean, "do you think the simulation is an accurate reflection of what would happen on a real PCB?")

---Joel

LDO Spit!

The good old LM7805 makes a nice 5V and works as a TV transmitter too. What more could we want.

Given that they made no attempt to compare their simulation to a real board, the sim doesn't look very trustworthy to me.

Fig 3 shows voltage distributions for unspecified amplitude current pulses.

The assumption that the edge connector supply impedance is low screws everything up, don't you think.?

John