pours under BGAs

John Larkin · 2009-11-07T18:48:21+00:00

I'm final-tweaking an 8-layer board that The Brat laid out. There'sone Xilinx Spartan6 FPGA that we use almost all the pins of, and Inoticed that its power pours are very cut up.ftp://Here's the "before" 1.2v core voltage pourftp://Notice the cut-off peninsula feeding from the right, which reallyisolates the bypass caps to the left.I tweaked this to...ftp://by futzing with the via pad stack, the pour parameters, and by pushingtraces and vias around - very tedious - to open up some floodchannels.We're using 1mm pitch BGAs, 6 mil design rules, and the bgavia is 10mil drill, 18 od.We'll have to ping some board houses to see what sort of design rulesand vias they can do nowadays without the cost exploding. We'realready getting quotes like $1600 for 5 boards in one week.Any thoughts on this? What are you guys doing to get good floods underdense BGAs?We're using dumbell pad+via combos on all the connected balls exceptthe outer rows. It would be fabulous to eliminate the vias, namely todrill the BGA pads. Is this ever done?The Brat is still learning PCB layout, and I'm a simple engineer. Iwonder if some real layout expert close to San Francisco could come upand give us some pointers, for money or beer.John(back to checking)BOARD STATISTICS REPORT -- 26D150A_51.pcb -- Sat Nov 07 10:40:04 2009Job Design Time: 291:31Part Types: 66Parts TopSide: 516 BottomSide: 0 Total: 516Drilled pads: 478 Undrilled pads: 2659 Total: 3137Via Name : STANDARDVIA Via Count : 727Via Name : POWERVIA Via Count : 123Via Name : BGAVIA Via Count : 946Signal Nets: 714Connections Routed: 1116 Partially 373 Unrouted: 35 Total: 1524Plane Nets: 1Connections Routed: 40 Partially 599 Unrouted: 20 Total: 659Routed Connection Length (inches) X: 907.86 Y: 813.33 Total:1721.19 Unrouted Connection Length (inches) X: 1741.48 Y: 1275.80 Total:3017.28 Number of copper clearance errors: 0Number of Routing Layers: 8Size...

Nov 07, 2009 20 Replies

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krw 16 years ago

isolated/decoupled and

Again, I haven't had one[*] of mine fail because of decoupling but I've fixed others that have. I also said that there were decoupling issues with the IBM 3080 series of mainframes (the only TTL models they ever made, for good reason). ECL is so much easier. ;-)

[*] A *multi-layer* board - did have some wired boards fail because of crappy decoupling.

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pours under BGAs

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pours under BGAs

this is getting crazy

Sending out a PCB for quotes

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