another Chinese stackup

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Some people don't read fab notes. They use whatever material is laying around.

The outer diels are about 10 mils, and I specified 20. Well, it's better then the 4 mils I got from PCBWAY.

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Still, 10 is useless for my circuit.

I wonder why they use such thin outer dielectrics.

Reply to
John Larkin
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PCBWay loves ignoring my fab instructions, even when they say they will hon or them. I use specific rules and features in my soldermasks, and they see m to toss out my mask layer and make up their own about half the time. The price makes it attractive, but for serious stuff I find it worth my money to buy domestic.

Reply to
DemonicTubes

torsdag den 14. januar 2021 kl. 23.53.24 UTC+1 skrev John Larkin:

if you go to McDonalds and order a burger do you expect them to make a special shape and color of wrapping just for you ?

because it makes it possible to do LVDS/DDR etc. impdances without traces that are wider than the parts ..

Reply to
Lasse Langwadt Christensen

Am 14.01.21 um 23:53 schrieb John Larkin:

Because most people want to escape from a pin grid array with 50 / 100 Ohms transmission lines.

Reply to
Gerhard Hoffmann

Oh, they do ghastly solder masks.

The thing about domestic is to make sure it really is.

Reply to
John Larkin

I don't expect to get a hot dog.

I don't think that is their motivation.

Reply to
John Larkin

Controlled impedance boards with random dielectrics?

More likely because it's cheap somehow.

Reply to
John Larkin

fredag den 15. januar 2021 kl. 00.44.34 UTC+1 skrev John Larkin:

why do you think it is random?

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Reply to
Lasse Langwadt Christensen

Because they don't follow fab drawings even when they say they will.

Reply to
John Larkin

fredag den 15. januar 2021 kl. 01.55.38 UTC+1 skrev John Larkin:

did you follow their ordering instruction and tick all the right boxes, or did you just put in a note on the drawings and hoped they would see it?

Reply to
Lasse Langwadt Christensen

Don't know. Purchasing buys stuff. I just make drawings.

Their solder mask was terrible too. And their drill registration.

But that stack is weird.

Cheap, and worth it.

Reply to
John Larkin

Well yeah, you order as proto, you get proto service.

So many people on the internet these days, complaining about them, and JLCPCB, and asking questions like, what about stackup, and can I do X... You paid five bucks for the whole damn thing, of course no you can't do those things!

For getting a proto, that's able to break out fine pitch BGAs, it's an amazing deal. It even comes with features that used to be special, like plated and routed slots. Trying to use it for something it's not made for (special impedance, high voltage/current, etc.) is only deluding yourself.

I did a custom 4 x 2oz Cu, 20/20/20 x FR4 build from PCBCART, like $200/10. Way cheaper than Advanced or others. Looks great. And they use the soldermask that doesn't just flake off. In fact, heh, sheesh, my chronically dull hobby knife here doesn't even scratch it. I need to get actually-useful blades for that already...

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Design 
Website: https://www.seventransistorlabs.com/ 

"John Larkin"  wrote in message  
news:6hi10gdbhidqtpm0pe9olu00v6j24549mm@4ax.com... 
> 
> https://www.dropbox.com/s/z2g2e503xjn7b8u/Z496_Chinese_Stack.jpg?raw=1 
> 
> Some people don't read fab notes. They use whatever material is laying 
> around. 
> 
> The outer diels are about 10 mils, and I specified 20. Well, it's 
> better then the 4 mils I got from PCBWAY. 
> 
> https://www.dropbox.com/s/p3vpbaofzqurebz/Z462_PCB_Way_2.png?raw=1 
> 
> Still, 10 is useless for my circuit. 
> 
> I wonder why they use such thin outer dielectrics. 
>
Reply to
Tim Williams

.
  1. > Way cheaper than Advanced or others. Looks great. And they use the

What are you talking about breaking out fine pitch BGAs??? I've been looki ng at the numbers with JLC and they are better than some, but You aren't go ing to route 0.4 mm BGAs with their capabilities. I'd have to look at the specs in detail for a given footprint, but I don't think they can even do 0 .5 mm BGAs. Pretty much anyone can do 1 mm and most can do 0.8 mm pitch BG As, but I don't think they are considered fine pitch. Exactly what dimensi ons are you talking about JLC being able to do?

Some of their capability page was not clear and I asked in the chat. I was told for my 12 year old design with 10 mil drills they would likely bump t hat up to a larger size. The language on their page talks about up sizing annular rings to 0.15 mm (6 mil). That gives via sizes of about 0.6 mm or

24 mil. How are you going to route a 0.5 mm BGA with 0.6 mm via pads? Doe s that work? For the 0.5 mm CPG196 Xilinx wants via pads of 0.27 mm (11 mi l) and via holes of 0.15 mm (6 mil). I don't see that happening on a JLC b oard with 0.2 drill and 0.4 mm pad minimums. Looks like they can't even do 0.8 mm pitch with 0.25 mm drill and 0.51 mm via pad size.

I did find that LCSC has very good prices on Xilinx parts, ~$5 for XC6SLX16

-2FTG256C in a 1 mm spaced BGA package. Still not easy to route on a tight board with all the vias, but possible without using a more expensive board process. I don't think the rest of my board could be built by JLC as they would not have the parts in stock... not all of them anyway.

--

Rick C. 

- Get 1,000 miles of free Supercharging 
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Reply to
Rick C

JLC lists 0.25mm BGA and 0.127mm distance:

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So that is a pitch of 0.377mm

Reply to
Klaus Kragelund

Of course one then needs to place a track somehow :-)

Internal layers is 0.09mm width and also 0.09mm clearance. So that adds

0.18mm, so 0.6mm pitch should be possible
Reply to
Klaus Kragelund

I buy real x-acto #16 blades in bulk. They don't last long hogging epoxy-glass.

Speaking of which, I decapped a TO247 mosfet yesterday and ruined three dremel cutters before I even saw a wire bond. Had to finish it off with a tiny carbide dental burr, slowly.

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--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

I've done the EPC GaN fets, tiny BGAs, with PCBWAY boards. Their resolution and plating are fine. Their standard stackup is weird and their solder masks are all over the place, at this scale.

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Production wants mask-defined pads for these parts, and you have to pay someone good to make those.

--

John Larkin      Highland Technology, Inc 

The best designs are necessarily accidental.
Reply to
jlarkin

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oking at the numbers with JLC and they are better than some, but You aren't going to route 0.4 mm BGAs with their capabilities. I'd have to look at th e specs in detail for a given footprint, but I don't think they can even do 0.5 mm BGAs. Pretty much anyone can do 1 mm and most can do 0.8 mm pitch B GAs, but I don't think they are considered fine pitch. Exactly what dimensi ons are you talking about JLC being able to do?

was told for my 12 year old design with 10 mil drills they would likely bum p that up to a larger size. The language on their page talks about up sizin g annular rings to 0.15 mm (6 mil). That gives via sizes of about 0.6 mm or 24 mil. How are you going to route a 0.5 mm BGA with 0.6 mm via pads? Does that work? For the 0.5 mm CPG196 Xilinx wants via pads of 0.27 mm (11 mil) and via holes of 0.15 mm (6 mil). I don't see that happening on a JLC boar d with 0.2 drill and 0.4 mm pad minimums. Looks like they can't even do 0.8 mm pitch with 0.25 mm drill and 0.51 mm via pad size.

LX16-2FTG256C in a 1 mm spaced BGA package. Still not easy to route on a ti ght board with all the vias, but possible without using a more expensive bo ard process. I don't think the rest of my board could be built by JLC as th ey would not have the parts in stock... not all of them anyway.

Why would I care about the pitch of the BGA pads they can achieve? They do n't show any vias for breaking out the connections, do they? That's the p art of using BGAs that requires finer PCB processes. No point in working w ith 0.4 mm pitch BGAs if I can only access the first row or two of I/Os.

--

Rick C. 

+ Get 1,000 miles of free Supercharging 
+ Tesla referral code - https://ts.la/richard11209
Reply to
Rick C

You have more than one layer, so the real issue is how much does it take to place one track

--
Klaus Kragelund
Reply to
Klaus Kragelund

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looking at the numbers with JLC and they are better than some, but You are n't going to route 0.4 mm BGAs with their capabilities. I'd have to look at the specs in detail for a given footprint, but I don't think they can even do 0.5 mm BGAs. Pretty much anyone can do 1 mm and most can do 0.8 mm pitc h BGAs, but I don't think they are considered fine pitch. Exactly what dime nsions are you talking about JLC being able to do?

I was told for my 12 year old design with 10 mil drills they would likely bump that up to a larger size. The language on their page talks about up si zing annular rings to 0.15 mm (6 mil). That gives via sizes of about 0.6 mm or 24 mil. How are you going to route a 0.5 mm BGA with 0.6 mm via pads? D oes that work? For the 0.5 mm CPG196 Xilinx wants via pads of 0.27 mm (11 m il) and via holes of 0.15 mm (6 mil). I don't see that happening on a JLC b oard with 0.2 drill and 0.4 mm pad minimums. Looks like they can't even do

0.8 mm pitch with 0.25 mm drill and 0.51 mm via pad size.

C6SLX16-2FTG256C in a 1 mm spaced BGA package. Still not easy to route on a tight board with all the vias, but possible without using a more expensive board process. I don't think the rest of my board could be built by JLC as they would not have the parts in stock... not all of them anyway.

don't show any vias for breaking out the connections, do they? That's the p art of using BGAs that requires finer PCB processes. No point in working wi th 0.4 mm pitch BGAs if I can only access the first row or two of I/Os.

to place one track

I don't think that is the limiting issue at all. To break out the pins on inner rows of a BGA requires vias to route on another layer. Once on other layers you don't have pads in the way, so routing is freer. On the compon ent layer you have pads and vias so the only routing is from pad to via whi ch is typically a very short route of no consequence and routes from the ou ter row which is a gimme and the next to outer row which can be routed dire ctly given the trace space limitations you are addressing. If those dimens ions are too limiting to route the next to outer row on the same layer, via s can be used.

So the real issue is being able to get vias between the pads to route on ot her layers. This must be addressed on any BGA of more than 16 pins. I see m to recall some BGAs that have a break between the outermost rows and the inner rows to facilitate routing without vias between the pads. I think th ese are still hard to route as the open space needs to support an awful lot of vias.

--

Rick C. 

-- Get 1,000 miles of free Supercharging 
-- Tesla referral code - https://ts.la/richard11209
Reply to
Rick C

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