some PCB trace resistances

That's not a wide range, for miscellaneous PCB traces.

Are those trace widths as designed or as measured? Narrow traces get undercut during etch and if the 5 mil were nearer to 4 mil that could explain what you are observing.

piglet

Not to mention varying tin and solder reflow thickness. I once got a shipment of PCBs made with 2-oz copper, rather than standard 1-oz; that created discrepancies!

They are supposed to take care of that! The 5 mil is the design/Gerber value. I could measure the actuals with difficulty.

All our boards are SMOBC these days, with ENIG on the pads and vias. We don't mask vias, except under BGAs.

I don't mind what I'm seeing here. We specified 1 oz min and looks like we got it.

Trace impedances were close, even though I didn't specify impedance control.

Our next challenge will be some tiny mask-defined pads for the 4-ball EPC ganfets. PCBWAY did that very badly, so we'll pay for Gorilla boards next batch.

This sounded scary: "ENIG can be expensive, and at times can result in what is commonly known as

between the gold and nickel layers that can result in fractured surfaces and faulty connections."

Enig seems to be free nowadays. The gold is just micro-inches thick, and it's only on the pads. It solders fabulously and looks great, and it's perfectly planar, great for BGAs. It doesn't tarnish in storage, like a solder-coated board.

I think I saw a little ENIG black pad effect once, a long time ago, but it seemed to be cosmetic. Soldering dissolves the few micro-inches of gold, and the resulting joint is inspectable.

I really like not solder masking the vias too. Every via is an easily probe-able test point, or an easy kluge. I wanted to solder mask topside vias under BGAs but not mask the bottom side, for probe-ability, but the PC houses don't want to do that. They say that crud can be trapped in a via that's solder masked on only one side.

We solder mask (tent) the vias because we sometimes have an environment favorable to condensation and this keeps pads (or other vias) from connecting thru the condensation. We miss the ability to probe on the vias, however.

Copper thickness alone is +/-20%, on top of that all the other tolerances

Cheers

Klaus

On the same board? From one edge to another? Or maybe at any point on the board compared to some other point? Does it depend on the size of the board? Is there a variation in Cu thickness across a 1" x 1" board?

An inquiring mind wants to know. This is very interesting.

Thanks!

What horrible process did you read that from?

Fortunately, there's a ton of information out there, readily available. Sadly, a lot of it isn't applicable to current-day commodity production.

Some people still think RoHS is a conspiracy for planned obsolescence...

A lot of whom are even on this newsgroup...

FYI, phosphorous isn't even used anywhere in production (so is probably present in the < 0.01% range as a trace impurity), but the phenomena can manifest from Au-Sn and other intermetallics in the joint. It's just a metallurgical thing. You need enough Sn/Pb to dissolve the Au (and maybe Ni base layer, if possible; Ni solubility is very low though), and then it's fine.

This isn't a problem on normal parts, but can be relevant to CSPs and LGAs, where the solder volume is very small, and the joint is molten for a very short time (seconds).

It used to be a problem on regular SMTs, until people realized, oh duh, we don't need 30u in hard gold over the whole freaking board. (And this was common knowledge in the, I don't know, early 80s, if that gives you any perspective.) :-)

Tim

Haven't seen data on distribution so you'll have to measure that yourself.

It's an ionic diffusion problem, so the deposition rate can vary greatly over the board area, but most especially in concavities.

That 12 mil vias are even possible (in 62 mil thick PCB), let alone 8 mil vias being /practical/, is quite remarkable, a testament to the leveling capability of the plating baths -- both the additives that control the distribution of electric and ionic charge, and the voltage/current profile used to do the plating. (A "high throw" bath prevents buildup on outside corners, preferring more deposition into the barrel of deep vias.)

This isn't unique to PCBs. ICs have to deal with big ranges of inhomogeneity. This is partly why IC resistors are so s**te (+/-30% say). The more specific reason is the uncertainty in diffusion (dopant concentration and thickness, process time*temp). More accurate layers can be made by sputtering, for example. The most precise, repeatable and finely detailed structures are, I think, made by molecular layer deposition, where a precursor molecule is condensed onto the initial surface, preferentially, so as to form a monolayer. The molecule is then transformed into its target form, depositing a ~perfect atomic layer of substance. Repeat or alternate substances until complete.

Tim

Here's a detail from the board we just got. It's 6 layers, SMOBC and ENIG, unmasked vias.

The little nasty near C123 is OK: this is a free "solder sample" board. At least they didn't punch a big hole in the ss board, which some people do.

We got the first two assembled boards this morning. I checked all the power supplies and what analog things I could without any uP or FPGA code; no problems. My embedded programmer guy had the ARM running code and executing serial commands in about an hour. This is an ST processor that we've never used before.

Tomorrow I might get our first Xilinx config code. The +1V supply has basically no load with the FPGA unprogrammed, so it's doing rude burp things.

I would have rejected that PCB - the solder mask between e.g. U44.8 and U44.9 and the via next to them is too thin. Same near e.g. U44.6, U44.12 U44.21 and U44.29. When re-flowing, the solder on the pads could easily be sucked into the via, possibly leaving not enough solder for a proper pad to pin junction. To minimize (ground?) impedance I'd rather add extra via's, e.g. to the lower right of U44.8 and U44.9. Note: the PCB manufacturer might have increased the via mask holes, causing this problem. Your design rules might be fine.

Unmasked via's are great, but mind the solder mask!

Arie

Right, solder mask web width violation.

Don't recall if JL's archaic system (PADS) even has that check.

This is also a point in favor of rounded pads: the soldermask corners on quad-pack pins can have this violation, even though the copper clearance is more than adequate. Setting rounded corners (say 30% of pad width) or round solves that.

Regarding the vias, I set a design rule that all bottom-side testpoints are partially tented on top (i.e., solder mask expansion 3 mil from hole edge -- not much pad left, and very unlikely to end up with mask clogging the hole), and full pad on bottom (3 mil from pad edge). All others, are either 3 mil from hole edge, or fully tented. This saves a lot of congestion, with respect to soldermask clearances, and looks very neat.

I set testpoints automatically so I know that all nets are testable when doing this, I'm not leaving any vias tented that I may need later.

That drool of copper between C123 and TPG14 is lovely. Sample indeed.

Also all the 90/45 angled segments, except that one dumb angle just off the bottom of C131. :^)

This is more of a problem with leaded. SAC305 migrates very little. Another point in favor of RoHS.

If this were something faster, that would be an excellent precaution.

An STM32 won't notice at all (but you can if you want to).

Tim

The Brat and I did that layout fast, in shifts. I wanted to keep inductances down, so I probably pushed vias a bit too close to pads in the fast parts. But the assembled board looks fine. And works!

PADS works fine too.

I like any-angle (beeline) routing for fast stuff. Some people object to that for no rational reason.

This board is ROHS.

Here's the thing soldered.

Looks like the solder really wants to slurp under the parts. I don't see any on the vias.

Yes, really looks OK. But no guarantee for next batch of PCBs - please set a minimum mask width! (Sorry to keep nagging, had too much troubles and discussion with production over tiny problems like this. And with the PCB MFG).

Arie

If we do a rev B board, I'll open up the gaps a bit. With a little luck, we'll never do a rev B board.