Yes, John, why _did_ you suggest 470uF? My understanding is that you want to use the smallest reservoir cap you can get away with consistent with your design goals, to minimize the current through the rectifiers.
Not that I'm an expert on this -- I've only had two designs on the market that get their power from the mains, and those used wall-warts.
Hi John,
Further to our discussion a few days back, I measured the 33W psu of my own design.
As mentioned, I expected around a 2ms conduction period and the oscilloscope pics confirm this.
This also confirms that 8ms is a sensible period to use when calculating ripple voltage for 50Hz psus ( as I originally suggested ).
I did note that you mentioned the use of a 470uF reservoir cap though. I only need 100uF in my design ( might nearly have got away with 68uF
- no problem actually if I wasn't looking for a 'universal voltage' input ) .
What's the reason for 470uF ? It will result in less ripple - and ( by first principles ) also result in a shorter conduction angle for the input current.
Graham
Pics posted in a.b.s.e
I read in sci.electronics.design that Pooh Bear wrote (in ) about 'Ping John Woodgate - conduction angle in smps', on Fri, 7 Oct 2005:
Meeting immunity requirements re voltage dips and interruptions. Must be in EN 55024 somewhere (assuming your product is ITE). Clause 4.2.6, perhaps.
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