Hi,
I am using a coolMOS mosfet and this appnote: "Application Note CoolMOS CP (AN_CoolMOS_CP_01_Rev1.1.pdf"
from this page: "
says to minimize the PCB layouts gate to drain capacitance as much as possible. The layout I have for an Hbridge, has the bottom side of the PCB with polygons of copper for the fet's drains, and then the gate traces are on the top side (half of Hbridge shown and gate drive signals not routed yet):
"
The TO-220 packages are the coolMOS fets, the IC10/IC2 SOIC-8 packages are the fet driver IC's, and the IC48/IC50 SOI-8 packages are optocouplers. I think this layout will have a fair bit more gate to drain capacitance than the recommended one in the pdf (the middle pins of the TO-220 are the fet drain)
From the pdf, when using fast switching and high voltage, the high V/us transients on the drain trace can couple into the gate drive circuit, also because the the "coolMOS" mosfets have low internal gate to drain capacitance they are susceptible to this more apparently. I am using max 600Volt Drain to source voltages, and minimum 15ns switching, so that would be 40kV/us transients on the drain I guess, which could interfere with the gate to source voltages. I used large PCB area for the drain signals as the currents are fairly high. Should I change the layout to use lower PCB gate to drain capacitance?
cheers, Jamie