MOSFET Drain-Source Leakage

You're right, it's all thermal. Judging from your 1 to 10uA numbers above, I'd hazard a guess that your NMOS is way too big for your application.

What is the highest VDS you must handle? Dumping current?

...Jim Thompson

"Gary Pace"

Leakage = 1nA max.

... Phil

I second Jim's opinion... do you need such a big fet?

John

"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Jim :

Thanks.

I chose a low Rds FET because in the initial design I was concerned about reset time on the integration, but I since changed the arrangement and I now have 10's of us, so I can select a FET based on low leakage.

Gary

Can you balance it with a diode (small schottky?) to +V? (Fun stuff, I've balanced FET inputs between diodes.. equal 1N914s aren't a bad high impedance voltage divider! ;-) ) Tweak the CCS's "zero-intercept" current? Yeah yeah, it varies with temperature, right?

How much current are you dropping, anyway? I mean, I've done some pretty clean stuff with 2N4401's, like the monostable I'm fond of posting:

Mind you that was *all* within 5% -- it looked clean on the scope, no need for anything more precise than that.

Other things I've had excellent results with include a diode-gated CCS operating at 1 to 4.5e6 Hz in one range (1Hz being basically the diode/CCS leakage current, which was something in the nA range at that temperature). Same sort of idea, the current just doesn't change as suddenly. If it did, the duty cycle would be pretty impressive, like 1 second rise time, this on the leakage current.

AIUI all your dB values need to be doubled, for currents.

It's 20*LOG(ratio) for voltages and currents

and 10*LOG(ratio) for power

...Jim Thompson

Whoops! It was late ;)

Tim