LVC Series Gate Input Capacitance

NOR.http://focus.ti.com/lit/ds/symlink/sn74lvc2g02.pdf

Ci page 4, electrical characteristics, 5pF

Yes, and then D, given the uncertainty of the IC input capacitance, wiring capacitance, etc., select a larger value, say 33pF, and reduce the resistor as needed.

NOR.http://focus.ti.com/lit/ds/symlink/sn74lvc2g02.pdf

Arrrgh... :( I missed that. I think I skimmed over the datasheet too fast. 2x too!.

I suspect it's customary to have Cin on a datasheet for digital logic. I should have distrusted my skimming..

Thanks..

D from BC

Ahh..the more predictable, less design time approach.

I wonder how often engineers use logic Cin to make some RC lag when needed. I suppose if the RC tolerance is wide enough, it should be ok to do..

However, there's uncertainty, testing required* and more math that might peeve a designer on the clock.. I can see why overwhelming the Cin with 33pF is a quicker solution.

D from BC

Not that you can rely on that value. I think it's listed as a "typical" capacitance, but in the sense that we typically assign 5pF of input capacitance to an input node, without really knowing, and more or less taking adding in some of the capacitance from whatever might be connected to the input node.

Where I've carefully measured the capacitance, mostly older HC types, etc., it's typically been much less than 5pF. I'd expect newer LVC stuff to be even less. That's why I suggested swamping the 5pF with external capacitance. Furthermore, if one's input is from an off-baord source, with a connector, etc., it's a good idea to add a second resistor, from your RC, to the gate input, so your RC can act as a spark-discharge filter and give the gate's protection a better chance.

BTW, many LVC datasheets now say 4pF.

Not the case but interesting and may pop up one day..

Like this /static \\ / >----R1------long run-----------R2---+----->[74LVC gate] | RC=(R1+R2)*C1 C1 Where C1>>Cgate | Gnd

For a long run and a little delay.

D from BC

No, like this:

static / / / pcb components external >---- R1 --+-- R2 -----> [74LVC gate] signal | _|_ source | --- C1 connector | Gnd

Anyplace handling is involved is vulnerable.

Ah... I get it now. The static gets attenuated by 2 RC sections.

Some trivia... Would that be called a Pi filter?

D from BC

That term is usually reserved for versions with inductors.

In the end you'd have to decide how accurate your delay has to be. Relying on Cin is something I never do. One day a "new and improved" chip comes out, the new guy being blissfully unaware of a hairy design signs the ECO, the purchasing guys order the reels and a few weeks later some hollering is heard in production. Followed by some more hollering in the board room.

Double cascaded RC filter?

Yeah, it looks risky to use the SN74LVC input cap. to create some lag. I thought about using a pot to account for variations..

A cheesy way to create some lag.

Adjust until warm and cozy?? :)

D from BC

That sure sounds quite posh.

We used to call that "rubber engineering" ;-)