Isolated variable resistor function?

Except that the simplest way of decoding Manchester 2 pretty much uses John's scheme. He re-invented the constant cross-section roller when he should have re-invented the wheel.

-- Bill Sloman, Nijmegen

For a design with a single clock, that clock must run at 256MHz to get the required 3.9ns resolution. A designer using an FPGA would probably choose this method.

Now consider a design with a 16MHz clock feeding a delay line with sixteen 3.9ns taps. A multiplexer can select any of the taps, which gives the required 3.9ns resolution. The highest frequency in the design is only 16MHz though. A designer of an ASIC would probably choose this method.

An ASIC allows the delays of the taps to be matched reasonably well. A phase detector can compare the input and 16-tap delayed clocks and this can be used to trim the total delay to be exactly 1 period of the input clock.

For more information, try searching for Delay Locked Loop.

(As an aside, if I was doing this in an FPGA I would use one of the onboard 5GHz transceivers to get 200 ps PWM resolution.)

Regards, Allan

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No, I had in mind long/short pulses, not a constant bit rate. Long/shorts can convey a clock and data on a single wire, and receive separation takes just an RC. Manchester takes a bit more work to receive.

I first invented a Manchester decoder (and encoder, and a supervisory control system that sold megabucks) when I was an EE undergrad. Deriving the receive clock is easy: a transition detector followed by a one-shot of 0.75 times the bit period.

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Sure. But there are a lot of single wire serial communication protocols, and re-inventing Morse code isn't exactly something to boast about.

-- Bill Sloman, Nijmegen

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So find a (cheap!) 1-wire dpot that solves Joerg's problem. Quit being bitchy and do something useful.

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But the MSP430 Timer D will lock tightly at a wide range of oscillator frequencies, with up to 25MHz inputs but down, so far as I can now tell, a few kHz. That is a huge dynamic range of operation and fixed delay taps won't cut that mustard.

Bill's comment about varying the current to adjust delays (twisted ring osc, that he mentioned) might also be applied (given my ignorance) to adjust delay taps -- but I simply cannot buy the idea that it could do so, and do so accurately enough, over such a wide operating range. It just sounds insane to imagine.

Jon

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A ten thousand to one range - 25MHZ to 2.5kHz - would imply changing the tail currents from 1mA to to 100nA.

That does happen to be one thing that you can do with well-matched bipolar transistors on a single integrated circuit - 60mV off the base- to-emitter voltage cuts the current by a factor of ten, and four decades takes 240mV. The text-book examples show plots that cover a rather wider current range.

-- Bill Sloman, Nijmegen

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Cheap parts aren't really my thing. I approve of them in principle, and use them when I can, but throughout my career I designed in a lot more parts with tightly specified high performances that weren't all that cheap.

One of your typically courteous and constructive contributions.

-- Bill Sloman, Nijmegen

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I just looked at the manual and it says 8MHz-16MHz for x16, 8MHz-25MHz for x8

that an the involved describtion of how to change frequencies, I think point to a delay line

something like a long delayline, first pick the right tap to get a full period then pick the taps get close to x16 or x8, adjust as you go

afair the DCM in a spartan3 FPGA does phase shift etc., with a delayline with 45ps per tap

-Lasse

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I see your point. I'll bet that the fancy subcycle resolution does not work below a 1 MHz basis PWM counter clock. It is a rather special mode and undoubtedly has constraints.

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Or some logic in the corner of a FPGA.

Long/short is how 1-wire works, and probably several other things.

Sinclair Research was using long/short mark followed by long/short space to record data on audio cassette in 1982. Mark length was one bit, space length the next, (thus, the bit-rate was data-dependant, the average was about 1300 bits per second obvoiously a pattern like

Not when John was an undergrad. It took a lot of relays, then. ;-)

The 0.75T one-shot works in an FPGA, too.

Well, 74-series TTL. Ironically, it's fairly recently that relays started getting really good, small/fast/reliable/cheap enough to use in signal circuits instead of CMOS multiplexers.

"Invented?" Bwahahahahaha! That's like Gore claiming he invented the Internet. Your "invented" method can be found in ancient textbooks. ...Jim Thompson

I didn't say I invented it first, just that I invented it. Before the internet, it was hard to access prior art. It's not shocking that lots of people independently discovered the same circuits. We sold hundreds of supervisory control systems using the Manchester-with-CRC comm protocols I defined. I designed all the control, i/o, modems, power supplies, and color graphic display controllers (quite a novelty at the time, when a mediocre Conrac color monitor cost $2400.) I wrote the PDP-11 RTOS, too. All that was fun, pioneering stuff for an undergraduate. I'm a systems/circuit designer, which isn't so much about inventing pieces as it is about putting pieces together the best way, a step or two up the abstraction stack from semiconductor physics.

Got a link to the Manchester prior art that you refer to?

I'm looking ;-)

As for the "transition detector", you do it all-in-one... rising AND falling edge-triggered one-shot. ...Jim Thompson

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=A0 =A0...Jim Thompson

It's a bit depressing when an undergraduate with free access to a university library declares that he couldn't access prior art.

That's exactly what you were at the university to learn about, but you went off and re-invented the wheel instead. You seem to have done just enough academic work to pass the exams, rather than learning a bit about the subject you had enrolled to study.

Re-inventing the wheel is pioneering?

But it does help if you have some kind of deeper understanding of the pieces you are putting together.

-- Bill Sloman, Nijmegen