Isolated variable resistor function?

Thanks. I learn something new every day :-)

The "takes no resources" part is not true. Every ever so tiny project needs to be managed, reviewed, documented, regression-tested, ECO-released, and on and on. Changing the thread diameter of a screw can easily cause many manhours of extra work.

Right the first time. "better than I" is an elliptical construction for "better than I would". (And even if there were a dative case in English, "I" isn't the object of the preposition.)

Now where's Rich Grise with the comma police. ;)

Cheers

Phil Hobbs

It's a

"Takes unavailable resources" means "takes resources that are not available", i.e. you and IBMJARG are in violent agreement.

Cheers

Phil Hobbs

It's a

I meant what Keith wrote :-)

As for unavailable resources, our drill sergeant had a solution for that. Sometimes he hollered "The day has 24 hours and if that's not enough there's still the night!"

(Atmel

ranging

=20

solve=20

Well, as I pointed to before, take a look at Figure 19-2 in the Family User's Guide, found following from here:

It is behaviorally diagrammed as a fast clock generator followed by your basic /1 /2 /4 /8 divider. It picks off of the IDEX divider against the regular clock sources, so on that level it looks like a normal multiplier. It includes an "in-lock" bit, TDHLKIFG, to inform you when lock is achieved.

It also runs completely free. No lock, no care about another oscillator, at all. So all that makes me think they actually have a fast internal DCO of some kind, but where it can optionally be locked to a lower speed crystal source.

Some words may relate to what you were saying, Tim. I see this:

In regulated mode, the high-resolution generator produces 8 or 16 equidistant events per timer input clock cycle. Regulation is enabled by setting the high-resolution calibration enable bit TDHREGEN. The high-resolution generator tracks changes of the timer input clock after locking to the timer input clock frequency. Locking is indicated by setting the lock interrupt flag TDHLKIFG. As long as the high- resolution generator is not locked, the interrupt flag TDHUNLKIFG is set.

If the timer input clock is out of the frequency range of the high-resolution generator, then the fail-high interrupt flag (TDHFHIFG) or the fail- low interrupt flag (TDHFLIFG) is set.

If the TDHREGEN bit is cleared, the continuous regulation is stopped and the high-resolution frequency enters free-running mode. The latest settings are kept.

There is no datasheet yet and so I can't look at related specs that might help elucidate any better. I assumed that they folded in Nat Semi technology (they are doing this with their work on FRAM, too) to reach 256MHz in their process.

It's a little odd on the MSP430, as it goes upstream of their "extremely low power" selling point (valid and well-made.) If they were doing this and keeping most of the high clock rate stuff tightly contained in small region of the die, perhaps it would still be 'congruent.' But they use it to drive an entire timer counter and this also means fast compare logic, as well. So it starts to look like more die space is involved than less and I have to imagine current draw will be unusually high then.

Still, it is another selling point corner, I suppose.

Jon

There is a dative case in English.

But thanks for saving my bacon. :)

Jon

There are various schemes to try to make English a strongly inflected language, and they're all doomed. Importing Latin case names doesn't make it so.

Cheers

Phil Hobbs

I meant hardware resources. If it's only done on power-on, it doesn't count. ;-)

That's covered by "Even the validation is a piece of cake.". Since it only occurs on power-on, the complexity of interactions with other processes goes

Sure, but that's hardware. ;-)

It's a

See above.

In a department meeting once, my manager said that he had "good news and bad news". "The good news was that everyone will be working half-days from now on." "Now the bad news, there are 24 hours in a day." He wasn't kidding but I'd already been working 12x6-1/2 for months by that time and I only had a few months to go. ;-)

It's a

Ah, missed that one. Keith's and my posts crossed in the ether. Miss Thistlebottom hereby goes back into retirement. ;)

Cheers

Phil Hobbs

I see this quote from TI: "the TMS320F280x devices offer a TI proprietary high-resolution PWM mode that provides approximately 6 additional bits of resolution beyond the standard time-base resolution..."

Is that what you meant?

Jon

of

"Adding that feature is JTAB" which means "it's just a test and a branch."

Says some simplistic single-quadrant multiplier might work. Still interested? Or is problem already "solved"? ...Jim Thompson

modulation.

Well, I am likely going to use the digital potmeter. 30c is hard to beat. I just thought that maybe someome knows an analog miracle optocoupler that can comply with 1V excitation. That would have reduced a 2-chip solution to 1-chip.

Simulating some control stuff for it right now. But, the Weber is heating up so in a few minutes there will be a scent of barbecued beef ribs wafting through the neighborhood. Followed by a shotglass of Forsthaeusler that I brought back from Germany on Thursday. 80-proof but smooth as can be:

Couldn't believe it, there is next to no burning sensation on the way down. This stuff is great.

modulation.

I have hand-matched 2-channel opto-couplers to make a truly linear transfer function, but it's a PITA.

Digital pots are hard to beat. If you can afford an extra OpAmp you can side-step the absolute tolerance of the digital pot.

I did the sushi bar (Ra) after seeing "2016"... required two Sake martini's to calm me down >:-)

I drink Drambuie ;-) ...Jim Thompson

On a sunny day (Sun, 26 Aug 2012 14:51:57 -0700) it happened Joerg wrote in :

Talking about drill sergeants, we once had to do a 5 km run. IIRC I dropped to the back and took a shortcut. When back he found out, and decided I had to do the whole distance again... To make sure I actually did it, he came along, must have over-estimated his condition, I went as fast as I could and he could not keep up, after all he had just done the drill. That really pissed him I think. But he never bothered me again :-)

So much for mil training...

enabled

clock

indicated

is

(TDHFHIFG)

stopped

latest

This part: "In regulated mode, the high-resolution generator produces 8 or 16 equidistant events per timer input clock cycle" means what it says.

It should not be construed as meaning there's a 256MHz clock anywhere: 16 phases of a 16MHz clock is not the same as a 256MHz clock.

Regards, Allan

But there could well be - in modern microcontrollers there is often a clock up around there, due to the way a standard crystal frequency is multiplied up by a PLL then divided down again to get the specific clocks required.

.2

on

xt

le

at

do

ur

r,

ed

es 8 or 16

ion is

DHREGEN.

er input

ng is

the high-

TDHUNLKIFG

of the

flag

on is

ode. The

ly

ll

s.

But a twisted ring oscillator is a cheaper way of creating the effect; you vary the oscillation frequency by varying the current - and this the delay - through each of the gates forming the ring.

-- Bill Sloman, Nijmegen