Sure but the optimum plane assignment can't be made independent of the interplane distances. The above discussion means nothing without knowing (or, better, specifying) the dielectric thicknesses.
This antiquated technology doesn't seem to support an "edit post" feature reliably, an addendum is what's available.
I grew up with the ability to modify posts. I'm really spoiled, I know
The SoC in the OP's design is a somewhat more modest affair; the mfgr in question is even kind enough to provide a reference on how to free them all on a single layer. Luxurious of them, I know!
I can set those distances to whatever works for the stackup I choose. What you are you trying to say? You don't need to use the same thicknesses for each stackup. This is not a test question with arbitrary constraints.
-- Rick C. ++ Get 1,000 miles of free Supercharging ++ Tesla referral code - https://ts.la/richard11209
Do they say what design rules are required? Not needing microvias is a big plus!
-- Rick C. --- Get 1,000 miles of free Supercharging --- Tesla referral code - https://ts.la/richard11209
That was a bare board, no caps installed. The SMA connector scopes the
3.3 volt power plane against ground. You can figure out the capacitance from the charging curve. In my experience, adding any bypass cap anywhere on the plane just makes it look like a bigger capacitance. With good ground and power planes, it doesn't much matter where you put the bypass caps. The parasitic inductance of the cap and vias don't seem to matter either; the plane itself is the high frequency bypass.It's a "solder sample" board, which is why it has a hole punched in it, to make it unusable.
I have the PCB for a cheap TDR, but I haven't had time to make it work.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
What's the trace width? They are running two traces beween balls.
Only three balls deep.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
eaglebone Black on a chip (OSD335x-SM), and a 20MHz ADC (AD9238)... they do n't all fit on one side of the board, their datasheets all want ground plan es under them... if I put the ADC on the bottom of the board and have a Pow er Plane under it, is that close enough to having a ground plane under the part? or can a ground pour under the IC take the place of a ground plane?
two planes are being coupled together?) the power plane is just as good as a ground. But that's only true if you do not have significant currents ca using local voltage variations in the power plane.
All the current flowing through the power plane has to flow back out again through the ground plane (or another power plane).
Kirchoff's Law means that you have to think about current loops, not one-wa y current flows.
cuitry connected at just one point to prevent digitally induced currents fr om messing with the ADC.
It's better though of in terms of controlling the path followed by particul ar current loops. There's rarely just one.
G1 P1 P2 G2 S2
Printed circuit manufacturers don't seem to offer 5-layer boards.
-- Bill Sloman, Sydney
Dumbass, I'm saying that you didn't make any sense when you proposed the "better" stack up without specifying interplane spacing at the same time. It matters.
hat you are you trying to say? You don't need to use the same thicknesses for each stackup. This is not a test question with arbitrary constraints.
It matters in what way? Setting the interplane spacing depends on the many unspecified requirements. The interplane capacitance can be maximized by making the spacing as thin as possible. But there is no reason to sacrific e other unspecified design aspects like controlled impedances unless you ca n't meet the unspecified PDS requirements otherwise.
So give me the requirements and I'll give you the plane spacings... dumbass .
Why do you have to call people names just because you don't understand what they are saying?
Are you only twelve?
-- Rick C. --+ Get 1,000 miles of free Supercharging --+ Tesla referral code - https://ts.la/richard11209
Sure but I wanted to see evidence that the location of the cap didn't matter. I'd do it but we don't have a TDR, or boards with a nice SMA connected neatly to the planes.
Understood. You could still use it to demonstrate the issue.
I want a rather good one. An 1180x/SD24 should be good enough. A network analyzer seems like gilding the Lilly and perhaps more complicated than its worth.
You're obviously too stupid to understand the basics.
Only five and a half times over.
Trust me.
I have an 11802 on my bench, and a bunch of SD24s and other heads. The SD24 can do TDR and TDT simultaneously. You can also use one TDR channel as a trigger out to things, and snoop the results on the other.
SD14 is cool too, a dual channel 3 GHz HiZ probe. Something like 0.25 pF at the probe tips.
A VNA can be used to fake TDR, with some FFT math or something. But response doesn't go down to DC.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
:
the
What you are you trying to say? You don't need to use the same thickness es for each stackup. This is not a test question with arbitrary constraint s.
any unspecified requirements. The interplane capacitance can be maximized by making the spacing as thin as possible. But there is no reason to sacri fice other unspecified design aspects like controlled impedances unless you can't meet the unspecified PDS requirements otherwise.
But krw is much too stupid to illustate where Rick C has "failed to underst and the basics", and rather too stupid to understand that what Rick C did p ost didn't illustrate any such failure.
ass.
hat they are saying?
Which is to say that krw is well into his second childhood and going backwa rds.
-- Bill Sloman, Sydney
I believe you but my cow-orkers don't know what a nice guy you are.
At a *much* higher cost. Not to mention complexity.
I just sheared up my PCBWAY proto board, and I'm evaluating some microwave-grade edge-launch SMA connectors. This boardlet has one inexpensive Amphenol connector and one super-cheap Mueller.
They both look pretty good, with small inductive bumps. Looks like I nailed the 50 ohm CPW impedance pretty close, with the Saturn software.
Maybe the inductive bumps are actually my necked-down trace. I can fix that.
The first cursor dot in on the semi-hardline and the second is midway along the trace.
I've got some more connectors to try, and some other layout variations. I love TDR.
Maybe you can get an 11801 from a big-name broker.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.