Shielding (reducing capacitive coupling) between a high dv/dt node and a ground plane.

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5V/ns is not a high dV/dt. MOSFET drivers routinely drive MOSFETs through their switching voltage in 10ns or so if you let them. A modest 60V swing gives you 6V/ns in this case. A more dangerous situation is a 800V swing in 10ns, that's 80V/ns. I recently completed a design with these specs, using an ordinary two-sided PCB. I'm not sure swinging high-voltage ground planes are a good idea, and in laying out HV PCBs over the years, I have yet to find a place where one made good sense. They can make sense on paper, looking at the design, e.g., where an isolator, gate supply and gate driver swings with an n-channel pullup MOSFET's swinging source pin, etc., but when push-come-to-shove on the PCB board layout, nope. I just keep the swinging high-voltage stuff away from the low-voltage stuff. I also like to put the low- voltage stuff on the underside of the board, away from all the tall high- voltage power components. Given that most of that is smt parts, I can have a ground plane on the top, above those parts, providing some shielding from the already distant high dV/dt high-voltage parts. Besides, you want to minimize the total design capacitance associated with any high dV/dt nodes. Piece of cake.

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6V/ns is not a high dV/dt. MOSFET drivers routinely drive MOSFETs through their switching voltage in 10ns or so if you let them. A modest 60V swing gives you 6V/ns in this case. A more dangerous situation is a 800V swing in 10ns, that's 80V/ns, or 80kV/us, as they like to spec it.* I recently completed such a design, using an ordinary two-sided PCB. I'm not sure swinging high-voltage ground planes are a good idea, and in laying out HV PCBs over the years, I rarely find places where one makes good sense. They can make sense on paper, looking at the design, e.g., where an isolator, gate supply and gate driver swings with an n-channel pullup MOSFET's swinging source pin, etc., but when push-comes-to-shove on the PCB board layout, nope.

I just keep the swinging high-voltage stuff away from the low-voltage stuff. I also like to put the low-voltage stuff on the underside of the board, away from all the tall high-voltage power components. Given that the low-voltage parts are smt, I can have a ground plane on the top, above those parts, providing some shielding from the already distant high dV/dt high-voltage parts. Besides, you want to minimize the total design capacitance associated with any high dV/dt nodes. Piece of cake.

• The most difficult issue is finding isolators that can handle at least 50kV/us high dV/dt.

Do you have any low-impedance signals that travel with the sensitive node? If so, you could put a patch of driven guard pour on layer 7.

John

Not quite sure what you mean so I'll desribe teh circuit more. The has a small RM4LP SMT pulse transformer with a center tapped secondary and two diodes for FW rectification. Then there is 400 ohms of pulldown resistance of capacitance to smooth the thin pikes from the rectification process.

The concept is similar to figure 38 in this appnote

When the transformer is energized, it peak charges a cap through a 1n4148 diode and that cap powers the gate driver when the gate is low. The 400 ohms pulldown is actually two

200 ohms in series and with a 320pF cap from between them to floating "ground" for filtering the signal going to the input pin on the fet driver.

The center tap of the secondary goes directly to the S pin of a high side fet.

The secondary of the transformer, the four SOD123 diodes, six 0805 components, a sioc-8 IC, a 7343 smt tantalum cap, and a sot-23 TVS are conncted with 10 mil traces in a very tight layout between the secondary pads and the mosfet. The high current source trace that connects to the low side fet is intentionally routed away from these components.

The problem occurs when the low side fet turns on and pulls the S pin down at ~6V/nS (600->0 in 100ns). All the components hooked to the secondary get pulled down with the source pin.

When I probe with a differential probe, I get these measurement with the - side on the center tap and the + to the following points.

1) Center tap (testing the common mode noise immunity of the probe). clean 2) Source pin of the FET. clean (low impedance connection) 3) Anodes of the two rectifier diodes. 1V tall (same for both) 4) Cathode if the two rectifier diodes. 10V tall.. hmm it's not coming from the transformer through the diodes as first suspected. 5) center point between the two 200 ohm resistors (in pin of fet driver) 8V tall..hmm should be half of the 10V tall pulse.... :( 6) Fet driver power pin (floating cap) clean 7) Fet driver ground. Clean Fetdriver output clean edges following the input signal (Vin > 2V its high) 8) To gate pin. same as driver output with slightly slowed edges due to gate drive resistance.

The amplitude of the pulses goes up and down with bus voltage. It also gets worse when I clip in the differential probe. More stuff swinging and radiating I suppose.

Any more thoughts?

thanks for the input so far.

Its eating my cake. :( LOL i think the problem is that the dv is 600V. even iwth 4pF of capacitance the current injected is I = C dv/dt = ~24mA. That through 200 ohms is enough to bias the fet driver input signal on. I guess I need to get the capacitance down to below 1pF.

Please find more info in response to John response.

Thanks for the input. If you have any further input I'm all ears.

Reading it again I think I figured out what you were getting at and it was along the same lines I was thinking.

All the high dv/dt traces are on layer 8 (bottom). The capacitance I suspect is from the plane on layer 6. if a clear the plane in layers 6 and

5 under this part of the circuit and put a small pour under the circuits in question. that should shield them. That plane can be connected to the source pin of the mosfet which is a low impedance source and the floating "ground" for those circuits.

Win suggest the opposite approach. Clean everything from around those nodes that could capacitively couple and make the capacitive footprint small. I think his concern is swing a large'ish 1"x1" plane with the high dv/dt will cause radiation problems.

An actual schematic would help.

John

See alt.binaries.schematics.electronics

Either might help. Cutting away several layers of copper can reduce capacitance substantially; a driven guard can in theory reduce the bad capacitance to zero.

I can't find your post to a.b.s.e. Maybe my spam filter chucked it.

John

+600v -+- .-------. | .-----| | ||---'

-----. || .' |gate |----||

I just checked, its out here. the title is "From SED: Shielding (reducing capacitive coupling) between a high dv/dt node and a ground plane."

Thanks for the input.

Thanks.

Yes, a copper pour under the "gate driver" stuff, connected to the source of Q1, might help defend the driver bits from ground.

Transformer capacitance can be a problem, too.

John

The transformer has a electrostatic shield between primary and secondary that is connected to emitter pin of Q1. Fixed that subtle problem but ocmpletelymissd the board coupling issue. I guess a way to test it is to lift the componends off the board and wire them in air to see if the problem goes away.

Thanks

Got a spare board? Chop out the square inch or whatever of driver circuit and use that as a babyboard. Bootstrap one of its ground pour layers to Q1.

John

even better idea. Thanks