I am working on an 8-layer board that has two stripline sections. Gnd- sig-gnd, gnd-sig-gnd type of structure. OK, so when a chip on top "launches" a differential signal into the lower stripline, I use two through-hole vias for the signals, but also two vias to connect the ground planes together, at that point. Then when the signals get to the connector to go off the board, I do the same thing again. We have a consultant that says I should put through hole vias everywhere to connect the two stripline structures together. I think this is not required, I gave an example of a differential pulse generator hooked up to a scope, you use two coaxes for this, grounded at the source end, and grounded at the destination end. You don't strip the jacket away to connect the two coax grounds together the whole way. So why should I add ground vias everywhere? Once the signal is launched into its stripline environment, what is happening in the other stripline is of no interest, and IMHO connecting them can cause more problems that it purports to solve. Who's right, who's wrong, and why?
I tend to agree with your consultant. Not because I am also a consultant but because we have to consider external fields getting in. Plus possibly something leaking out and creating a bad-hair day at the EMC lab. The outer sections of your respective gnd-sig-gnd structures might not be part of a larger plane. If not then they can become loop antennas with the loop length being the distance between vias. Loop length determines the efficiency of such unwanted antennas, or their capability to carry undesired RF energy in and out.
It depends a bit on what's inside. If this is a DC summing node there isn't so much to worry. But if it's RF lines then I would spring for some vias.
Howard Johnson started this weird compulsion about return currents. It makes no sense. The capacitance between the huge ground planes essentially glues them together at high frequencies, as it does ground and power planes. Adding vias close to signal vias, in order to provide a return current path, is by no means necessary; there are most likely plenty of plane-plane vias all over the board already.
Treat the ground planes, and any power planes for that matter, as solid, equipotential structures, which they will be if close and reasonably via'd or bypassed to one another. Again, plane-plane capacitance keeps them tight at high frequencies.
Thanks for your input. I agree for high frequencies. But a bit stream has frequency content down to almost DC, esp if we stress the patterns... I don't know what to do, this power supply/PCB stuff is rapidly turning into theology.
How wide are those planes? If they are all full ground planes, meaning over an inch or so wide, I'd agree with John. If they just cover the trace plus some margin I'd side with your consultant. Need some more info here, like a sketch or something.
BTW you can usually also use power planes as "free" shield planes. As long as there are no rogue consumers tied into them.
I think it does make sense, with the caveat that the "return current" is generated simultaneously with the "signal current" as a signal propagates down a trace (some people seem to have the mistaken notion that there's no return current until the signal current makes it to a load or whatever).
Howard's buddy Eric Bogatin has some convincing calculations that demonstrate the planes are only decent capacitors at *inconveniently* high frequencies, e.g., UHF and above (obviously it depends on the plane spacing).
There is a danger that if you get all those vias too close to the stripline itself, you may have dropped the transmission line's impedance enough to matter since you're building "square coax" rather than a stripline. On the other hand, such construction is useful for improved isolation (hence the kissing cousin, coplanar waveguides).
I doubt you'd second the recommendation, but I would suggest the OP should go take one of those week-long signal integrity (or similar) courses from Johnson, Bogatin, etc. with the money he's currently spending on a consultant.
Far-away vias and bypass caps keep the planes equipotential at low frequencies, and the plane capacitance keeps them stiff at high frequencies, and there's tons of overlap.
Right, and very little science. Fact is, so many people have so many bypassing and routing strategies precisely because, on a multilayer board, practically any scheme works. We break lots of "expert" rules and do picosecond stuff that works fine. The only things we have to be especially careful about are termination of edge-sensitive stuff and trace-trace crosstalk. Bypassing and "return currents" aren't big issues.
As an edge propagates, it clearly charges successive patches, call them "squares" for convenience, of the trace. And as each square charges, current is clearly dumped into the ground plane. But that current doesn't know where the driver chip is... it's just a zot of current that spreads out in all directions and eventually finds its way home. The ground plane looks like, well, a big ground plane.
TDRing a microstrip that runs over a ground-plane slit is not dramatic, as certain parties would have you believe. Nothing much happens.
I've done a fair amount of TDR testing of power planes on multilayer boards (I occasionally install an SMA footprint on the board layout so I can TDR bare boards and look at plane noise on working boards.) As far as I can tell, with a 30 ps TDR step, parallel planes look like a couple of nF of perfect capacitance. And as you start to solder in bypass caps *anywhere* on the board, it starts to look like a bigger perfect capacitance.
Trace-trace isolation is worth attention. We've had trouble configuring Xilinx FPGAs because their CCLK pin is so fast and tender, tiny amounts of ringing and crosstalk can make configuration unreliable. I understand they may be adding slow Schmitts to the config pins in the future.
Gaaaaaccckk! Johnson's book is half good stuff and half nonsense. If you can tell which is which, you don't need the book.
Sure, but it certainly doesn't spread out *indiscriminantly* in all directions -- something like 90% of the total current that "returns" from a microstrip is concentrated within something like +/-3W under the microstrip trace itself. Hence the start of the perennial argument that you usually don't need to put cuts in ground planes -- in most situations the layout can be arranged to "contain" its own ground (return) currents.
This behavior can be inferred based on modeling the ground plane as a big grid of L's and C's -- no need to appeal directly to Maxwell's equations, even.
How big is the slit? I haven't done the experiment, but I'd be surprised if there wasn't a significant "bump" once the length and width of the slit are some tens of degrees of electrical length.
Thinking about it, I suspect you're correct that it's not as big a deal as it's often made to be in many "typical" systems, as least as far as signal integrity is concerned. (EMI is another matter... ) The picture often shown with the return currents going around the slit probably is misleading, since only the the low frequencies will take that route instead of just viewing the slit as a small capacitor and "jumping the gap."
But it's a *distributed* capacitor, so the problem is that some fast edge can't utilize any capactiance beyond that contained within, say, a patch whose radius is something in the ballpark of the distance a signal can propagate given the rise time of edge to do so.
I've read some of the papers from folks like Istvan Novak and Larry Smith at Sun, where they discuss being able to fix weird, inexplicable CPU failures and bus misbehavior simply by judiciously choosing the quantity, value, and placement of bypass capacitors (where the smallest value is well under a few nF). What most people seem to do -- myself included -- is to take the "carpet bomb" approach to bypassing, and it does seem to work just fine, but I've always figured that someone like Joerg or other good consultants have probably seen cases where some system has such random lockups and end up being able to trace them to, e.g., a harmonic of some system clock that happens to have a high power supply impedance (where the plane and the bypass capacitors are taken as part of the "power supply").
I think his book is better than nothing for most people. :-) What book would you recommend?
The old school favorite was something like the Motorola MECL design manual, no?
And most auto accidents happen within a mile of home. Of *course* the current is highest near the point it's injected into the plane.
Right. All that epoxy, not to mention other planes, essentially bypasses the slit.
OK, think of a pair of parallel pcb planes as a super-low-impedance, low-Q transmission line stretching away in all directions. The first thing a very fast point load sees is this line impedance, a fraction of an ohm. Additional bypass caps are seen after appropriate round-trip prop delays. That whole mess looks like a pretty good wideband short. TDRing a typical eurocard power plane, without and then with caps, I've seen no signs of edge reflections or capacitor resonances. I think the Q is just too low, lots of dielectric and copper skin losses for such an absurdly low equivalent transmission line impedance.
A CPU may jump tens of amps in Icc in nanoseconds, and its timings may be lunched if Vcc changes a couple of tenths of a volt. That's extreme, and has to be handled carefully. Planes don't store that sort of low-frequency energy.
I frankly don't know of one.
That was pretty good, but didn't talk about planes a lot, and the trace impedance equations were naiive... just try increasing trace widths and the calculated impedances go negative!
The folks in publishing figured this out long ago -- if you can make money printing books, why go to all the effort to learn what's printed when you can just pay an author some pittance to do so? :-)
For functionality, the best and easiest scenario is to following the chip maker's application note when designing the circuit board. For EMC design, the easiest scenario is to following the advice from your in-house EMC guru. He's the one that has to test the board and obtain the certifications. It's really his responsibility.
I have seen circuit boards made by some of the large manufacturers, like HP and Intel, for instance, that almost seem to be magic--It's like they have an EMI sponge built into them. I once asked an EMC guy from one of these companies how they did it. His answer was, "We follow Maxwell's equations". Yah right!
Good EMC design is mostly determined by trial and error, over the years, and then the theory is developed afterwards to explain why it works. If you're company is new at this and you don't have the expertise and you have to obtain certifications, you might have a lot of troubles ahead of you.
In regard to your question, though, my experience has been that it helps to have as many ground planes as possible and it doesn't help to be creative by making things like ground-plane islands or limit the number of ground-plane connections, etc.
The problem here is that every chip designer thinks his part is the center of the universe. So they say that it should have a string of various value bypass caps on every power pin, or that the two board ground planes should be connected only once, directly under their chip.
We always use one ground plane, and bolt it to the chassis in as many places as practical. We've passed every EMI test first try.
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