Question about partial multiplication result in transposed FIR filter

about

FPGA,

be

that

characteristic.

can we read that tutorial?

Kaz

--------------------------------------- Posted through

They are talking about an extreme level of optimization by sharing partial products between multiplies. Trouble is, each multiply is by a different coefficient *and* a different data value. But in each successive clock cycle the data moves to the next coefficient, so if any of the bits of the coefficients match, the result of the previous partial product can just be shifted into the appropriate location in the adjacent product calculation. It would be a bit tortuous to code and would nullify the utility of the hard multipliers available in many FPGAs. It might be worth while to do if you are designing an ASIC though.

I posed this before I read your link. I assumed right, but I didn't see the block diagram which shows all the multiplies happening on the same data at the same time. I've written FIR filters before, I should have remembered this. So the individual partial products can be shared across all the multiplies and added appropriately. I expect this assumes fixed coefficients which naturally make multipliers simpler.

A simple, and useful, transformation for a FIR or IIR filter for FPGAs is to switch from using one big summing node, with a series of delays before/after with tap offs and multiplies to having a single node feed forward/back to a series of nodes with simple adders. Since with the FPGA the registers at the outputs are free, this is the most efficient format. It also says that if the coefficients are constants, you have a possibility of optimizing some of the partial produces if building explicit multipliers.